D E T A I L E D A R C H I T E C T U R E
Data Device Corporation
SB-3642 Manual
Rev D – 4/19
17
Table 5. Velocity Characteristics
PARAMETER
UNITS
TYPICAL
MAX./MIN.
POLARITY
Voltage Range
V
4.0
VOLTAGE SCALING
(resolution dependent)
RPS/V
Typical TR (See Table 3)
SCALE FACTOR
Error
Scale Factor TC
Reversal Error
Linearity
Zero Offset
Zero Offset TC
Load
%
PPM/ deg C
%
% output
mV
uV/ deg C
k Ohms
10
100
1
0.5
5
15
20 (max.)
200 (max.)
2 (max.)
1 (max.)
15 (max.)
30 (max.)
10 (min.)
4.2.2 Built-In-Test (BIT) Output
The Built-In-Test (BIT) will flag Loss-of-Signal (LOS), Loss-of-Reference (LOR), Loss-
of-Tracking (LOT), and 180° phase error fault conditions. The BIT output is active low
and a logical OR of these four conditions. Any one or combination of these conditions
will assert the BIT output. These fault conditions are described in Table 6 below. Also,
excessive error is detected when the difference between the analog input and the
digital output exceeds approximately 100 LSBs of positive or 250 LSBs of negative
error (in the selected resolution), the BIT will be asserted.
Table 6. BIT Fault Conditions
Fault Condition
Description
LOS
Both SIN and COS inputs (S1-S3, S2-S4) must fall below 0.5 Vrms.
LOR
The reference input (RH-RL) must fall below 0.5 Vrms.
LOT
This condition occurs when the difference between the analog input and digital
output exceeds 100 LSBs in the positive direction or 250 LSBs in the negative
direction. This typically occurs when exceeding the maximum tracking rate or
during power up.
180° Phase Error
180° phase error input signal to reference input (false null) causes a BIT plus
kickstarts the converter counter to correct the error.
4.2.3 Synthesized Reference
The synthesized reference eliminates errors due to phase shift within the resolver
sensor of up to 45° between the reference and the signal inputs. This feature is built
into all input channels of this device.
