Data Device Corporation
SB-3642 Manual
Rev D – 4/19
14
4 DETAILED ARCHITECTURE
4.1 PCI Interface
The card provides a target 32-bit PCI interface, as defined in the PCI Local Bus
Specification, Rev 3.0, which operates at clock speeds of up to 66 MHz for
applications where a higher bus speed is desired. If a 33 MHz device was placed on a
66 MHz bus, the bus speed would be forced to slow down to 33 MHz. Although
resolver simulation may not require the additional bandwidth of a 66 MHz bus, the SB-
3642
66 MHz device allows the base CPU PCI bus to run at 66 MHz, enabling other
high-speed devices on the bus to take advantage of the higher bandwidth.
When using the card with the supplied Motion Feedback C SDK (SB-36030Sx) and
drivers there is no need to reference the PCI configuration registers.
Connection to the host is established through the card’s Pn1 and Pn2 connectors. PCI
64 bit extension is not supported, the PMC Pn3 for PCI 64 bit extension and Pn4 for
user I/O connectors are not populated on the card.
4.1.1 Use with 5V PCI Signaling
The PCI interface signals on the SB-3642
s3.3V or +5V signaling. The device
incorporates both 3.3V and 5V signal keying holes.
4.1.2 Register & Memory Addressing
The SB-3642
PCI interface contains a set of "Type 00h" PCI configuration registers
that are used to map the device into the host system. The configuration register space
is mapped in accordance with PCI Revision 3.0 specifications. These registers are
arranged such that all memory and register space may be addressed through a single
PCI function.
Configuration registers implement the Subsystem Vendor and Device ID, and control
the Fail-Safe operation of the device. There is one Base Address Registers (BAR)
used on the design of this card. All BAR mapping is located in PCI configuration
register space.
When using this card with DDC's driver and the API library software, the details of
these registers and memory addresses are abstracted from the user to provide an
easy-to-use High Level “C” programming environment.
