A x e l H a r d w a r e M a n u a l
v . 1 . 0 . 4
5
Power, reset and control
5.1
Power Supply Unit (PSU) and recommended
power-up sequence
Implementing correct power-up sequence for i.MX6 processors
is not a trivial task because several power rails are involved.
AXEL SOM simplifies this task and embeds all the needed
circuitry. The following picture shows a simplified block
diagram of PSU/voltage monitoring circuitry:
April, 2015
25/78
Axel CPU module
Carrier board
POWER
MANAGEMENT
CIRCUITRY
LI
C
E
LL
ON BOARD
PERIPHERALS
AND MEMORIES
MEMS
RTC
PSU
PMIC PF0100 E0
V
G
E
N
1
2V8 - 4V5
PMIC_PROG_GATE_CTRL
V
G
E
N
4
V
G
E
N
2
V
G
E
N
6
V
S
N
V
S
S
W
B
S
T
IN
P
W
R
O
N
*
R
E
S
E
T
B
M
C
U
*
S
T
A
N
D
B
Y
*
S
D
W
N
B
*
IN
T
B
*
V
D
D
O
T
P
S
C
L,
S
D
A
P
M
IC
_L
IC
E
LL
V
D
D
S
O
C
D
D
R
_1
V
5
1V
2_
E
T
H
V
D
D
H
IG
H
_V
P
H
V
D
D
S
O
C
_C
A
P
V
D
D
P
U
V
D
D
_A
R
M
23
_C
A
P
V
D
D
_A
R
M
01
_C
A
P
V
G
E
N
5_
2V
8
V
D
D
_B
U
S
_C
A
P
V
D
D
_S
N
V
S
_C
A
P
V
G
E
N
3_
2V
5
N
V
C
C
_P
LL
_O
U
T
S
W
4
V
D
D
C
O
R
E
NVCC_CSI_EXT
NVCC_EIM_EXT
NVCC_SD3_EXT
NVCC_LCD_EXT
RTC_VBAT
V
G
E
N
1
V
G
E
N
2
V
G
E
N
4_
1V
8
V
G
E
N
6
S
W
4_
xV
/1
.8
V
P
M
IC
_V
S
N
V
S
P
M
IC
_S
W
B
S
T
_S
U
P
P
LY
P
M
IC
_5
V
PMIC_PROG_VPGM
PMIC_PROG_SDA,SCL
1K
i.MX6
* Please refer to reset scheme
VIN
11
7
6
5
3
8
1
10
4
2
9
1
CPU_PORn (active-low) is driven
low
PMIC_PWRON signal is pulled-up
PMIC transitions from OFF to ON
state
PMIC initiates power-up sequence
needed by MX6 processor
CPU_PORn is released
