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Location

Zynq-7000 All
Programmable SoC:
Concepts, Tools, and
Techniques (CTT)

http://www.xilinx.com/support/doc
umentation/sw_manuals/xilinx14_
6/ug873-zynq-ctt.pdf

Zynq-7000 All
Programmable SoC
Software Developers
Guide

http://www.xilinx.com/support/doc
umentation/user_guides/ug821-zy
nq-7000-swdev.pdf

Building Embedded Linux
Systems By Karim
Yaghmour.

This book covers all matters
involved in developing software
for embedded systems.

Training and Docs
sections of Free Electrons
website.

Brief but still exhaustive overview
of the Linux and Embedded Linux
world

Tab. 1

: Related documents

1.8

Conventions, Abbreviations, Acronyms

Abbreviation Definition

BTN

Button

BELK

BORA Embedded Linux Kit

EMAC

Ethernet Media Access Controller

GPI

General purpose input

GPIO

General purpose input and output

GPO

General purpose output

PCB

Printed circuit board

Zynq Programmable Logic

Zynq Processing System

PSU

Power supply unit

RTC

Real time clock

SOC

System-on-chip

SOM

System-on-module

March, 2016

9/66

Содержание ARM Cortex-A9 MPCore

Страница 1: ...DAVE Embedded Systems www dave eu info dave eu Bora Embedded Linux Kit BELK Quick Start Guide ARM Cortex A9 FPGA CPU Module Ultra Line...

Страница 2: ...B E L K Q u i c k S t a r t G u i d e v 1 0 9 Page intentionally left blank March 2016 2 66...

Страница 3: ...ite and integration into BELK 17 2 4 2 Kit Contents 19 2 4 3 BELK Release Notes 19 2 4 3 1Version 1 0 0 19 2 4 3 2Version 1 1 0 19 2 4 3 3Version 2 0 0 20 2 4 3 4Version 2 1 0 20 2 4 3 5Version 2 2 0...

Страница 4: ...ironment 50 3 4 6 3Build the Yocto image 50 3 4 6 4Build additional packages 51 3 4 7 ConfigID 51 3 4 7 1Customer s action 52 3 4 7 2ConfigID values 52 3 4 7 3ConfigID hardware implementation on BORA...

Страница 5: ...figure the BORA BORAX system to boot from network 63 5 Appendixes 65 5 1 U Boot environment 65 Index of Tables Tab 1 Related documents 9 Tab 2 Abbreviations and acronyms used in this manual 10 Illustr...

Страница 6: ...to ISO 9001 standards 1 4 Disclaimers DAVE Embedded Systems does not assume any responsibility for availability supply and support related to all products mentioned in this manual that are not strict...

Страница 7: ...amages to other products not supplied by DAVE Embedded Systems that are caused by a faulty BORA BORAX module or BORAEVB BORAXEVB carrier boards 1 6 Technical Support We are committed to making our pro...

Страница 8: ...php Cate gory BoraX BORA Hardware Manual http www dave eu sites default f les fles bora hm pdf BORAX Hardware description http wiki dave eu index php Cate gory BoraX Hardware BORAEVB page on DAVE Emb...

Страница 9: ...l matters involved in developing software for embedded systems Training and Docs sections of Free Electrons website Brief but still exhaustive overview of the Linux and Embedded Linux world Tab 1 Rela...

Страница 10: ...B E L K Q u i c k S t a r t G u i d e v 1 0 9 Abbreviation Definition WDT Watchdog Tab 2 Abbreviations and acronyms used in this manual March 2016 10 66...

Страница 11: ...ed info for Vivado 2013 3 Minor fxes 1 0 4 November 2013 Minor fxes Added Vivado FAQ 1 0 5 November 2013 Fixed toolchain and rfs infos Added toolchain and rfs FAQs Added Appendixes section Minor fxes...

Страница 12: ...of this processor enables extensive system level differentiation of new applications in many industry fields where high performances and extremely compact form factor 85mm x 50mm are key factors Smar...

Страница 13: ...ate custom accelerators that extend system performance and better match specific application requirements BORA BORAX is designed and manufactured according to DAVE Embedded Systems Ultra Line specific...

Страница 14: ...runs on many different platforms x86 PowerPC ARM SuperH MIPS etc applications are portable by definition there are a lot of open source applications running on top of Linux that can easily be integra...

Страница 15: ...urable capabilities The PS and PL can be tightly or loosely coupled using multiple interfaces and other signals that have a combined total of over 3 000 connections This enables the designer to effect...

Страница 16: ...t provides all the necessary components required to set up the developing environment for configuring the system PS and PL at hardware level build the first stage bootloader FSBL building the second s...

Страница 17: ...application notes and reference designs released by Xilinx still refers to ISE suite Plus Vivado is still a little bit green and several bug fixes and improvements are introduced by every new release...

Страница 18: ...se of control and flexibility This could not be acceptable in many cases where engineers need to control and customize many aspects of the project to implement what is required by system specification...

Страница 19: ...BORA BORAX SOM BORAEVB BORAXEVB Carrier board AC DC Single Output Wall Mount adapter Output 12V 2 0 A MicroSDHC card with SD adapter and USB adapter 2 4 3 BELK Release Notes 2 4 3 1 Version 1 0 0 Fir...

Страница 20: ...to Daisy 1 6 BSP Release please refer to section 3 4 6 2 4 3 5 Version 2 2 0 Updates 1 Switched to Vivado 2014 4 2 Added board part for the BORA SOM which includes all the settings of the Zynq PS for...

Страница 21: ...F common mode capacitors to ground for further details eg connection and selection of the magnetics please refer to the Micrel KSZ9031RNX datasheet Yocto ubi utils command line Some Yocto ubi utils co...

Страница 22: ...ORAEVB Li te BORAEVB BORAEVB BORAEVB BORAEVB BORAXEVB U Boot version 2013 04 bel k 1 0 0 2013 04 bel k 1 1 0 2013 04 bel k 2 0 0 2013 04 bel k 2 1 0 2014 07 bel k 2 2 0 2014 07 bel k 3 0 0 Linux versi...

Страница 23: ...sed of a host machine and a target machine In a typical environment the host is used by the developer to cross compile the code that is to run on the target In our March 2016 23 66 HOST TARGET FSBL Bo...

Страница 24: ...System NFS by the host This strategy kernel image and RFS retrieved from the network saves time during the development phase since no flash reprogramming or removable storage SD usb pen drives extern...

Страница 25: ...r 3 2 1 2 Xilinx Software Development Kit The Software Development Kit SDK is the Xilinx Integrated Design Environment for creating embedded applications on Zynq 7000 All Programmable SoCs SDK is the...

Страница 26: ...er to the set of programs that allow the building of a generic application For applications March 2016 26 66 HW Specification Hardware configuration PS configuration PL configuration bitstream Vivado...

Страница 27: ...takes a lot of time and hard disk space To avoid this tedious task we suggest using a pre built toolchain as explained in the following sections 3 2 3 First stage bootloader FSBL The first stage boot...

Страница 28: ...ernel Linux kernel for Zynq processors is maintained primarily by Xilinx that constantly works in close cooperation with Linux community in order to push all the released drivers into mainstream kerne...

Страница 29: ...tructured build systems are the following OpenEmbedded http wiki openembedded net index php Main_Page Yocto https www yoctoproject org Buildroot http buildroot uclibc org BELK does not provide a fully...

Страница 30: ...e PC please refer to http www xilinx com design tools vivado memory htm zynq 7 000 The Git tool is used to download the BORA BORAX project files for Vivado from our public git repositories as describe...

Страница 31: ...n control which means that it s not possible to track changes to the project files making development and release management complicated and error prone The best solution to these problems is that we...

Страница 32: ...es of a bootloader during development is the capability to download the Linux kernel from the network This saves a lot of time because developer doesn t have to program the image in flash every time h...

Страница 33: ...ded with the Xilinx SDK usually installed into opt Xilinx SDK Vivado_version gnu arm lin bin Once the toolchain is installed create a a bash script env sh containing the following lines export PATH pa...

Страница 34: ...compiler is available on the root file system go for native compilation instead of cross compilation when you cross compile rely on static linking and avoid dynamic linking against the root file syst...

Страница 35: ...ng access to the Git repositories a ssh key is required Please follow the procedure reported below to generate the RSA ssh key we assume that the ssh package and the required tools are installed on th...

Страница 36: ...f the git directory of the repositories so the user can immediately get access to the development trees Uncompressing the archive enables access to the hidden git directories of the repositories to ge...

Страница 37: ...and building a Zynq project for BORA BORAX BELK provides an example Vivado project for BORA BORAX boards This project allows to generate the FSBL binary image generate the bitstream of a simple PL des...

Страница 38: ...For BORAX please replace bora_FSBL with borax_FSBL bora_wrapper_hw_platform_0 with borax_wrapper_hw_platform_0 bora sdk with borax sdk bora_wrapper bit with borax_wrapper bit The procedure is the fol...

Страница 39: ...ite with the following commands opt Xilinx Vivado 2014 4 settings64 sh4 vivado mode tcl source build_project tcl notrace tclargs bitstream 5 the build_project script allows the user to select BORA or...

Страница 40: ...om support answers 65145 html apply bora_repo patch AR65145_ps7_init_c patch on ps7_init c under bora_wrapper_hw_platform_0 apply bora_repo patch AR65145_ps7_init_tcl patch on ps7_init tcl under bora_...

Страница 41: ...e following files bora_FSBL elf which can be found in the project Debug directory N B check that the Partition Type for FSBL is bootloader bora_wrapper bit which is the bitstream generated by the Viva...

Страница 42: ...ata boards board_pa rts zynq sudo cp r boards board_parts zynq BORAX opt Xilinx Vivado 2014 4 data boards board_pa rts zynq launch the Vivado Design Suite GUI with the following commands opt Xilinx Vi...

Страница 43: ...and CAN_0 interfaces manually connect the FCLK_CLK0 signal to M_AXI_GP0_ACLK and save the block design from the sources tab select the BORA BORAX block design bora bd for BORA borax bd for BORAX as De...

Страница 44: ...rom the scripts directory from the BORA repository select File Export Export Hardware on the next window enable Include Bitstream and click OK now launch the SDK session to generate the FSBL clicking...

Страница 45: ...b ora_FSBL elf PROJ_DIR bora sdk SDK SDK_Export bora_FSBL Debug b ora_FSBL bin this step is board dependent configure the automatic binary generation on project build In Project Explorer right click o...

Страница 46: ...ogin into the system assuming that a local repository has not been created clone the remote U Boot git repository the b option is used to automatically checkout the current branch git clone git git da...

Страница 47: ...e Zynq development environment has been set up properly see section 3 3 2 for more details start the Linux development server and login into the system assuming that a local repository has not been cr...

Страница 48: ...rv tftp belk with the following commands cp arch arm boot uImage srv tftp belk cp arch arm boot dts bora dtb srv tftp belk 3 4 5 Booting the system via NFS Assuming that the CPU module is booting with...

Страница 49: ...s of the build environment including the target machine architecture through the MACHINE variable the development machine s processor use through the BB_NUMBER_THREADS and PARALLEL_MAKE variables and...

Страница 50: ...ted below mkdir belk cd belk belk curl http commondatastorage googleapis com git repo downl oads repo repo belk chmod a x repo belk repo init u git git dave eu dave bora bora bsp git b bora belk repo...

Страница 51: ...s belk build bitbake memtester The resulting packages the default format is ipk can be found inside build tmp deploy ipk 3 4 7 ConfgID ConfigID is a new feature of DAVE Embedded Systems products It s...

Страница 52: ...f the carrier board that hosts the SOM stored on the carrier board itself and read by the SOM at boot time An additional attribute is UniqueID which is a read only code which univocally identifies a s...

Страница 53: ...bytes OTP block on NOR SPI to store ConfigID and its CRC32 UniqueID and its CRC32 3 4 7 4 ConfigID software implementation on BORA BORAX U Boot integrates the software routines for reading and display...

Страница 54: ...igid fdt_uniqueid fdtaddr fi fi zynq uboot run loadfdt configid_fixupfdt Gem e000b000 Waiting for PHY auto negotiation to complete done Using Gem e000b000 device TFTP from server 192 168 0 13 our IP a...

Страница 55: ...following sections describe how to create a bootable SD card and how to configure the system for booting from SD 3 4 8 1 How to create a bootable MicroSD card This section describes how to create a ne...

Страница 56: ...se note that the CUT CUT Read bootmode register BootModeRegister Xil_In32 BOOT_MODE_REG BootModeRegister BOOT_MODES_MASK always init QSPI InitQspi QSPI BOOT MODE ifdef XPAR_PS7_QSPI_LINEAR_0_S_AXI_BAS...

Страница 57: ...n select Create Zynq Boot Image select Create New BIF file and insert path and name of the bif file in the Boot image partitions section click on Add to browse and add the following files FSBL in elf...

Страница 58: ...py the boot bin file to the microSD card FAT32 partition 3 4 8 2 How to configure the system for SD boot The S5 dip switch on the BORAEVB BORAXEVB carrier boards is used for configuring the boot mode...

Страница 59: ...http www dave eu sites default fles fle s bora hm pdf BORAX Hardware description http wiki dave eu index php Category B oraX Hardware BORA product page http www dave eu products som xilinx zynq XC7Z01...

Страница 60: ...tallation directory on Windows A Git tool e g for Windows MsysGit http msysgit github io These tools can be installed either on Windows or Linux operating systems However if you need to build U Boot o...

Страница 61: ...g against the root file system libraries build your application using the same cross toolchain when available used for building the root file system 4 7 Q do you provide some application notes A yes w...

Страница 62: ...feature Synthesis and or device xc7z020 1 Infos 1 Warnings 0 Critical Warnings and 0 Errors encountered synth_design failed ERROR Common 17 345 A valid license was not found for feature Synthesis and...

Страница 63: ...h launch_runs verbose file build_project tcl line 113 Vivado please check the permissions of the home user Xilinx directory and make sure that the actual user has full access to that directory ll d ho...

Страница 64: ...60 ethaddr MAC address of the target 00 50 c2 1e af af netmask Netmask of the target 255 255 255 0 gatewayip IP address of the gateway 192 168 0 254 netdev Ethernet device name eth0 rootpath Path to t...

Страница 65: ...fsbl_base 0x40000 gateway 192 168 0 254 header_base 0 hostname bora importbootenv echo Importing environment from mmc env import t loadaddr filesize ipaddr 192 168 0 89 jtag_vx run vxargs bootvx 0x20...

Страница 66: ...dr u boot_base filesize updatefdt sf probe 0 0 0 sf erase fdt_base filesize sf write fdtaddr fdt_base filesize updatefpga sf probe 0 0 0 sf erase fpga_base filesize sf write loadaddr fpga_base filesiz...

Страница 67: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information DAVE Embedded Systems BELK L S BXELK H S...

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