4M30 Camera User’s Manual
13
DALSA
03-32-10030-04
Data Signals
Table 7: Data Signal Definition
Signal
Description
D*0+, D*0-
Data bit 0 true and complement—Output. (Least significant bit.)
D*1+, D*1-
Data bit 1 true and complement—Output.
D*2+, D*2-
Data bit 2 true and complement—Output.
D*3-D*10+,- etc.
Etc.
D*11+, D*11-
Data bit 11 true and complement—Output. (Most significant bit.)
Digitized video data is output from the camera as LVDS differential signals using 4 Molex 60-pin
connectors on the rear panel (labeled “DATA 1 through DATA 4”). The data is synchronous and
is accompanied by a pixel clock and clocking signals.
Data Clocking Signals
Table 8: Clock Signal Descriptions
Signal
Description
,
PIXCLK-
Pixel clock true and complement. 40MHz—Output.
Data is valid on the falling edge.
HSYNC+,
HSYNC-
Horizontal sync, true and complement—Output.
HSYNC high indicates the camera is outputting a valid line of data.
VSYNC+,
VSYNC-
Vertical sync, true and complement—Output.
VSYNC high indicates the camera is outputting a valid frame of data.
2.6 Serial Communication
Connector and Pinout
The serial interface provides control of frame rate, integration time (shuttering), video gain and
offset, external trigger and external integration. For information on how to control these functions,
see Camera Operation, beginning on page 19. The remote interface consists of a two-wire (plus
ground) full duplex RS-232 compatible serial link, used for camera configuration, and two back
panel SMA coax connectors used for external trigger input and output.
IMPORTANT:
This camera uses the
falling
falling
falling
falling
edge of the pixel
clock to register data.
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