Dalsa 1M28-SA, Руководство пользователя

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1M28 and 1M75 User’s Manual PRELIMINARY 47
DALSA 03-32-00525-03
Nr. HEX BINARY Nr. HEX BINARY Nr. HEX BINARY Nr. HEX BINARY
158 2BD 1011110101 190 2B3 1100110101 222 2A9 1001010101 254 308 0001000011
159 17A 0101111010 191 167 1110011010 223 153 1100101010 255 211 1000100001
Figure 22: Captured picture with active 10bit LFSR
References:
[SMITH00] Douglas J. Smith, “HDL Chip Design”, 7. Auflage 2000 Doone Publications,
Madison, AL, S. 179 - 186
ISBN 0-9651934-3-8
Example: VHDL Code
signal REG: STD_LOGIC_VECTOR (9 downto 0);
signal DATAIN: STD_LOGIC;
SR10R: process (ICLK) -- 10 bit LFSR
begin
if (ICLK'event and ICLK='1') then
if (RESET = '1') then -- reset:shift register is loaded
with 1.
REG <= "0000000001";
else
REG <= REG(8 downto 0) & DATAIN;
end if;
end if;
end process SR10R;
DATAIN <= REG(2) xor REG(9);
LFSR_OUT <= REG;