Cypress S6J3200 Series, Руководство пользователя

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CHAPTER 21:Ethernet MAC
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 595
If the back_pressure bit is set in the Network Control register (ETHERNETn_network_control[8]) the
transmit block transmits 64 bits of data, which can consist of 16 nibbles of 1011
b
or in bit rate mode 64
times 1b, whenever it sees an incoming frame to force a collision.
3.3.
MAC Receiver Block
The MAC Receiver block checks for valid preamble, FCS, alignment and length, presents received
frames to the External FIFO Interface and stores the frames destination address for use by the address
checking block. If during frame reception, the frame is found to be too long, a bad frame indication is sent
to the External FIFO Interface. The receiver logic ceases to send data to RX Packet Buffer Memory as
soon as this condition occurs.
At End of Frame reception the MAC Receiver block indicates to the Ethernet MAC DMA whether the
frame is good or bad. The Ethernet MAC DMA will recover the current receive buffer if the frame was bad.
Ethernet frames are normally stored in DMA memory or to the External FIFO Interface complete with the
FCS. Setting the fcs_remove bit in the Network Configuration register
(ETHERNETn_network_configuration[17]) causes frames to be stored without their corresponding FCS.
The reported frame length field is reduced by four bytes to reflect this operation.
The MAC Receive block signals to the register block to increment the alignment, CRC (FCS), short frame,
long frame, jabber or receive symbol errors when any of these exception conditions occur.
If bit 26 is set in the Network Configuration register, CRC errors will be ignored and CRC erroneous
frames will not be discarded, though the Frame Check Sequence Errors statistics register will still be
incremented. Additionally if configured to use the Ethernet MAC DMA and not enabled for jumbo frames
mode, then bit 13 of the receive buffer descriptor Word 1 will be updated to indicate the FCS validity for
the particular frame. This is useful for applications such as EtherCAT whereby individual frames with FCS
errors must be identified.
Received frames can be checked for length field error by setting the length_field_error_frame_discard bit
of the Network Configuration register (bit 16). When this bit is “1”, the receiver compares a frame’s
measured length with the length field (bytes 13 and 14) extracted from the frame. The frame is discarded
if the measured length is shorter. This checking procedure is for received frames between 64 bytes and
1518 bytes in length.
Each discarded frame is counted in the 10-bit length field Frame Check Sequence Errors statistics
register. Frames where the length field value is greater than or equal to 0600
h
(1536) will not be checked.
3.4.
Checksum Offload for IP, TCP, and UDP
The Ethernet MAC can be programmed to perform IP, TCP, and UDP checksum offloading in both receive
and transmit directions which is enabled by setting bit 24 in the Network Configuration register for receive
and bit 11 in the DMA Configuration register for transmit.
IPv4 packets contain a 16-bit checksum field, which is the 16-bit 1’s complement of the 1’s complement
sum of all 16-bit words in the header. TCP and UDP packets contain a 16-bit checksum field, which is the
16-bit 1’s complement of the 1’s complement sum of all 16-bit words in the header, the data and a
conceptual IP pseudo header.
To calculate these checksums in software requires each byte of the packet to be processed. For TCP and
UDP this can use a large amount of processing power. Offloading the checksum calculation to hardware
can result in significant performance improvements.