CHAPTER1: Flash Memory
4. Registers
P E R I P H E R A L M A N U A L
August 31, 2015, S6E1Cx_MN710-00016-1v0-E
35
CONFIDENTIAL
4.4
Flash Interrupt Status Register (FISR)
The Flash Interrupt Status Register (FISR) indicates the interrupt status of the FLASH memory.
Register Configuration
bit
7
6
5
4
3
2
1
0
Field
Reserved
HANGIF
RDYIF
Attribute
-
R/W
R/W
Initial Value
-
0
0
Register Functions
[bit7:2] Reserved bits
The read values are undefined. Ignored on write.
[bit1] HANGIF: HANG Interrupt Flag
This bit is set to "1" when the Flash HANG status is detected. This bit is set to "1" with the rising edge of
HANG signal. This bit is cleared to be "0" by writing "1" to the HANGC bit in the FICLR register.
bit
Description
0
Flash HANG status is not detected. (Initial value)
1
Flash HANG status is detected.
[bit0] RDYIF: RDY Interrupt Flag
This bit is set to "1" when the Flash RDY status is detected. This bit is set to "1" with the rising edge of RDY
signal. This bit is cleared to be "0" by writing "1" to the RDYC bit in the FICLR register.
bit
Description
0
Flash RDY status is not detected. (Initial value)
1
Flash RDY status is detected.
