CHAPTER1: Flash Memory
4. Registers
P E R I P H E R A L M A N U A L
August 31, 2015, S6E1Cx_MN710-00016-1v0-E
31
CONFIDENTIAL
4.1
Flash Read Wait Register (FRWTR)
The Flash Read Wait Register (FRWTR) specifies the wait cycle for the flash memory.
Register Configuration
bit
7
6
5
4
3
2
1
0
Field
Reserved
RWT
Attribute
-
R/W
Initial Value
-
011
Register Functions
[bit7:3] Reserved bits
The read values are undefined. Ignored on write.
[bit2:0] Read Wait Cycle
Specifies the read wait cycle for the Flash Memory.
bit
Description
000
0 cycle wait mode
This setting can be used when HCLK is 10MHz or less.
001
0 to 1 cycle wait mode
This setting should be specified when HCLK is 20MHz or less.
010
Setting Prohibited
011
0 to 3 cycle wait mode (Initial value)
This setting should be specified when HCLK is more than 20MHz.
100
Setting prohibited
101
Setting prohibited
110
Setting prohibited
111
Fixed wait cycle mode
Notes:
−
When HCLK is more than 10MHz, the usage at the setting of RWT=000 is prohibited. At the setting
of RWT=000, ensure that HCLK does not exceed 10MHz anytime.
−
The wait cycle in fixed wait cycle mode is specified by FSYNDN register.