CHAPTER1: Flash Memory
4. Registers
P E R I P H E R A L M A N U A L
34
S6E1Cx_MN710-00016-1v0-E, August 31, 2015
CONFIDENTIAL
4.3
Flash Interrupt Control Register (FICR)
The Flash Interrupt Control Register (FICR) specifies the interrupt enable setting of the flash memory.
Register Configuration
bit
7
6
5
4
3
2
1
0
Field
Reserved
HANGIE
RDYIE
Attribute
-
R/W
R/W
Initial Value
-
0
0
Register Functions
[bit7:2] Reserved bits
The read values are undefined. Ignored on write.
[bit1] HANGIE: HANG Interrupt Enable
This bit enables the flash HANG status interrupt. When the HANGIF bit in the FISR register and this bit are
both "1", an interrupt to CPU is generated.
bit
Description
0
Flash HANG interrupt is prohibited. (Initial value)
1
Flash HANG interrupt is permitted.
[bit0] RDYIE: RDY Interrupt Enable
This bit enables the flash RDY status interrupt. When the RDYIF bit in the FISR register and this bit are both
"1", an interrupt to CPU is generated.
bit
Description
0
Flash RDY interrupt is prohibited. (Initial value)
1
Flash RDY interrupt is permitted.
Note:
−
Clear the corresponding bit in the FISR register before this bit is set to "1" to enable the interrupt.
