CY8CKIT-050 PSoC® 5LP Development Kit Guide, Doc. # 001-65816 Rev. *E
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Hardware
Figure 4-8. Schematic for Protection Circuit on 5-V Power Line
Figure 4-9. Schematic for Protection Circuit on 3.3-V Power Line
4.2.6.1
Functional Description of Circuit
The protection circuit will protect from a maximum over-voltage or reverse-voltage of 12 Volts. The
cut-off voltage on the 5-V line is 5.7 V and on the 3.3-V line is 3.6 V. This means, if you apply more
than this voltage level from the external board connector side, the p-MOS Q5 will turn off, thus pro-
tecting the PSoC and other on-board components. The current consumption of these protection cir-
cuits is less than 6 mA.
When voltage from the external connector is between 1.8 V and 3.3 V, the p-MOS Q4 conducts.
Because the voltage across R16 is less than the threshold voltage (Vth) of p-MOS Q6, it will turn off
and the p-MOS Q5 conducts, allowing voltage supply to the DVK.
When the external power supply exceeds 3.3 V, the p-MOS Q5 starts conducting. This eventually
turns off p-MOS Q6 at 3.6 V, protecting the DVK from over-voltage.
When a reverse voltage is applied across the protection circuit from the external connector side, Q4
P-MOS will turn off, thus protecting the components on the board from reverse voltage.
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