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CY4636 WirelessUSB™ LP Keyboard Mouse Reference Design Kit User Guide, Doc. # 001-70355 Rev. *A
Code Examples
Figure 5-19. Ghost Key Example
5.3.3.8
Interrupt Usage and Timing
In the RDK keyboard, the following interrupts have been enabled:
■
Row Port interrupt
■
Bind button interrupt
When either of the above interrupts occurs, its ISR sets the flag. The interrupt latency includes two
portions. The first portion is the time between the assertion of an enabled interrupt and the start of its
ISR, which can be calculated using the following equation:
Latency1 = Time for current instruction to Time for M8C to change program counter to inter-
rupt a Time for LJMP instruction in interrupt table to execute.
For example, if the 5-cycle JMP instruction is executing when an interrupt becomes active, the total
number of CPU clock cycles before the ISR begins would be as follows:
(1 to 5 cycles for JMP to finish) + (13 cycles for interrupt routine) + (7 cycles for LJMP) = 21 to 25
cycles.
In the example above, at 12 MHz, 25 clock cycles take 2.083 µs. The second portion is the time
between the start of the ISR and the set of the flag. For example, the row port interrupt (caused by
pressing any key) takes 19 CPU clock cycles for this portion. Therefore, the Latency2 equals to
1.583 µs for the 12 MHz CPU.
Consequently, the total latency for a button interrupt is La Latency2 = 3.667 µs.
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