CY22392
Document #: 38-07013 Rev. *D
Page 5 of 8
Electrical Characteristics
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
I
OH
Output High Current
[3]
V
OH
= V
DD
– 0.5, V
DD
= 3.3 V
12
24
–
mA
I
OL
Output Low Current
[3]
V
OL
= 0.5V, V
DD
= 3.3 V
12
24
–
mA
C
XTAL_MIN
Crystal Load Capacitance
[3]
Capload at minimum setting
–
6
–
pF
C
XTAL_MAX
Crystal Load Capacitance
[3]
Capload at maximum setting
–
30
–
pF
C
LOAD_IN
Input Pin Capacitance
[3]
Except crystal pins
–
7
–
pF
V
IH
HIGH-Level Input Voltage
CMOS levels,% of AV
DD
70%
–
–
AV
DD
V
IL
LOW-Level Input Voltage
CMOS levels,% of AV
DD
–
–
30%
AV
DD
I
IH
Input HIGH Current
V
IN
= AV
DD
– 0.3 V
–
<1
10
µ
A
I
IL
Input LOW Current
V
IN
= +0.3 V
–
<1
10
µ
A
I
OZ
Output Leakage Current
Three-state outputs
–
10
µ
A
I
DD
Total Power Supply Current
3.3V Power Supply; 2 outputs @
166 MHz; 4 outputs @ 83 MHz
–
100
–
mA
3.3V Power Supply; 2 outputs @
20 MHz; 4 outputs @ 40 MHz
–
50
–
mA
I
DDS
Total Power Supply Current in
Shutdown Mode
Shutdown active
–
5
20
µ
A
Switching Characteristics
Parameter
Name
Description
Min.
Typ.
Max.
Unit
1/t
1
Output Frequency
[3, 4]
Clock output limit, Commercial
–
–
200
MHz
Clock output limit, Industrial
–
–
166
MHz
t
2
Output Duty Cycle
[3, 5]
Duty cycle for outputs, defined as t
2
÷
t
1
,
Fout < 100 MHz, divider >= 2, measured at V
DD
/2
45%
50%
55%
Duty cycle for outputs, defined as t
2
÷
t
1
,
Fout > 100 MHz or divider = 1, measured at V
DD
/2
40%
50%
60%
t
3
Rising Edge Slew Rate
[3]
Output clock rise time, 20% to 80% of V
DD
0.75
1.4
–
V/ns
t
4
Falling Edge Slew
Rate
[3]
Output clock fall time, 20% to 80% of V
DD
0.75
1.4
–
V/ns
t
5
Output three-state
Timing
[3]
Time for output to enter or leave three-state mode
after SHUTDOWN/OE switches
–
150
300
ns
t
6
Clock Jitter
[3, 6]
Peak-to-peak period jitter, CLK outputs measured
at V
DD
/2
–
400
–
ps
t
7
Lock Time
[3]
PLL Lock Time from Power-up
–
1.0
3
ms
Notes:
3. Guaranteed by design, not 100% tested.
4. Guaranteed to meet 20%–80% output thresholds and duty cycle specifications.
5. Reference Output duty cycle depends on XTALIN duty cycle.
6. Jitter varies significantly with configuration. Reference Output jitter depends on XTALIN jitter and edge rate.
