CY14E256L
Document Number: 001-06968 Rev. *F
Page 3 of 18
Device Operation
The CY14E256L nvSRAM is made up of two functional compo-
nents paired in the same physical cell. These are an SRAM
memory cell and a nonvolatile QuantumTrap cell. The SRAM
memory cell operates as a standard fast static RAM. Data in the
SRAM is transferred to the nonvolatile cell (the STORE
operation) or from the nonvolatile cell to SRAM (the RECALL
operation). This unique architecture enables the storage and
recall of all cells in parallel. During the STORE and RECALL
operations, SRAM READ and WRITE operations are inhibited.
The CY14E256L supports unlimited reads and writes similar to
a typical SRAM. In addition, it provides unlimited RECALL opera-
tions from the nonvolatile cells and up to one million STORE
operations.
SRAM Read
The CY14E256L performs a READ cycle whenever CE and OE
are LOW while WE and HSB are HIGH. The address specified
on pins A
0–14
determines the 32,768 data bytes accessed. When
the READ is initiated by an address transition, the outputs are
valid after a delay of t
AA
(READ cycle 1). If the READ is initiated
by CE or OE, the outputs are valid at t
ACE
or at t
DOE
, whichever
is later (READ cycle 2). The data outputs repeatedly respond to
address changes within the t
AA
access time without the need for
transitions on any control input pins, and remains valid until
another address change or until CE or OE is brought HIGH, or
WE or HSB is brought LOW.
SRAM Write
A WRITE cycle is performed whenever CE and WE are LOW and
HSB is HIGH. The address inputs must be stable prior to entering
the WRITE cycle and must remain stable until either CE or WE
goes HIGH at the end of the cycle. The data on the common IO
pins DQ
0–7
are written into the memory if it has valid t
SD
, before
the end of a WE controlled WRITE or before the end of an CE
controlled WRITE. Keep OE HIGH during the entire WRITE cycle
to avoid data bus contention on common IO lines. If OE is left
LOW, internal circuitry turns off the output buffers t
HZWE
after WE
goes LOW.
AutoStore Operation
The CY14E256L stores data to nvSRAM using one of three
storage operations:
1. Hardware store activated by HSB
2. Software store activated by an address sequence
3. AutoStore on device power down
AutoStore operation is a unique feature of QuantumTrap
technology and is enabled by default on the CY14E256L.
During normal operation, the device draws current from V
CC
to
charge a capacitor connected to the V
CAP
pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the V
CC
pin drops below V
SWITCH
, the part
automatically disconnects the V
CAP
pin from V
CC
. A STORE
operation is initiated with power provided by the V
CAP
capacitor.
Figure 2
shows the proper connection of the storage capacitor
(V
CAP
) for automatic store operation. A charge storage capacitor
having a capacitor of between 68uF and 220uF (+ 20%) rated at
6V should be provided. The voltage on the V
CAP
pin is driven to
5V by a charge pump internal to the chip. A pull up is placed on
WE to hold it inactive during power up.
In system power mode, both V
CC
and V
CAP
are connected to the
+5V power supply without the 68
μ
F capacitor. In this mode, the
AutoStore function of the CY14E256L operates on the stored
system charge as power goes down. The user must, however,
guarantee that V
CC
does not drop below 3.6V during the 10 ms
STORE
cycle.
To reduce unnecessary nonvolatile stores, AutoStore and
Hardware Store operations are ignored, unless at least one
WRITE operation has taken place since the most recent STORE
or RECALL cycle. Software initiated STORE cycles are
performed regardless of whether a WRITE operation has taken
place. An optional pull-up resistor is shown connected to HSB
.
The HSB signal is monitored by the system to detect if an
AutoStore cycle is in progress.
If the power supply drops faster than 20 us/volt before Vcc
reaches V
SWITCH
, then a 2.2 ohm resistor should be connected
between V
CC
and the system supply to avoid momentary excess
of current between V
CC
and V
CAP
.
AutoStore Inhibit mode
If an automatic STORE
on power loss is not required, then V
CC
is tied to ground and + 5V is applied to V
CAP
(
Figure 3
). This is
the AutoStore Inhibit mode, where the AutoStore function is
disabled. If the CY14E256L is operated in this configuration,
references to V
CC
are changed to V
CAP
throughout this data
sheet. In this mode, STORE
operations are triggered through
software control or the HSB pin. To enable or disable Autostore
using an I/O port pin see
“”
on page 5
.
It is not permissible to
change between these three options” on the fly”.
Figure 2. AutoStore Mode
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