Cypress CY14B104LA, Техническое описание

Страница: 13 / 23

PRELIMINARY
CY14B104LA, CY14B104NA
Document #: 001-49918 Rev. *A Page 13 of 23
AutoStore/Power Up RECALL
Parameters Description
20 ns 25 ns 45 ns
Unit
Min Max Min Max Min Max
t
HRECALL
[19]
Power Up RECALL Duration 20 20 20 ms
t
STORE
[20]
STORE Cycle Duration 8 8 8 ms
t
DELAY
[21]
Time Allowed to Complete SRAM Cycle 20 25 25 ns
V
SWITCH
Low Voltage Trigger Level 2.65 2.65 2.65 V
t
VCCRISE
VCC Rise Time 150 150 150
μ
s
V
HDIS
[12]
HSB Output Driver Disable Voltage 1.9 1.9 1.9 V
t
LZHSB
HSB To Output Active Time 5 5 5
μ
s
t
HHHD
HSB High Active Time 500 500 500 ns
Switching Waveforms
Figure 11. AutoStore or Power Up RECALL
[22]
V
SWITCH
V
HDIS
V
VCCRISE
t
STORE
t
STORE
t
HHHD
t
HHHD
t
DELAY
t
DELAY
t
LZHSB
t
LZHSB
t
HRECALL
t
HRECALL
HSB OUT
Autostore
POWER-
UP
RECALL
Read & Write
Inhibited
(
RWI
)
POWER-UP
RECALL
Read & Write
BROWN
OUT
Autostore
POWER-UP
RECALL
Read & Write
POWER
DOWN
Autostore
Note
20
Note
20
Note
23
Notes
19. t
HRECALL
starts from the time V
CC
rises above V
SWITCH.
20. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware Store takes place.
21. On a Hardware STORE, Software Store / Recall, AutoStore Enable / Disable and AutoStore initiation, SRAM operation continues to be enabled for time t
DELAY
.
22. Read and write cycles are ignored during STORE, RECALL, and while VCC is below V
SWITCH.
23. HSB pin is driven HIGH to VCC only by internal 100 kOhm resistor, HSB driver is disabled.
[+] Feedback