Cypress CY14B104LA Скачать руководство пользователя | Manualshive

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PRELIMINARY

CY14B104LA, CY14B104NA

Document #: 001-49918 Rev. *A

Page 17 of 23

Ordering Information

Speed

(ns)

Ordering Code

Package
Diagram

Package Type

Operating

Range

20

CY14B104LA-ZS20XCT

51-85087

44-pin TSOP II

Commercial

CY14B104LA-ZS20XC

51-85087

44-pin TSOP II

CY14B104LA-ZS20XIT

51-85087

44-pin TSOP II

Industrial

CY14B104LA-ZS20XI

51-85087

44-pin TSOP II

CY14B104LA-BA20XCT

51-85128

48-ball FBGA

Commercial

CY14B104LA-BA20XC

51-85128

48-ball FBGA

CY14B104LA-BA20XIT

51-85128

48-ball FBGA

Industrial

CY14B104LA-BA20XI

51-85128

48-ball FBGA

CY14B104NA-ZS20XCT

51-85087

44-pin TSOP II

Commercial

CY14B104NA-ZS20XC

51-85087

44-pin TSOP II

CY14B104NA-ZS20XIT

51-85087

44-pin TSOP II

Industrial

CY14B104NA-ZS20XI

51-85087

44-pin TSOP II

CY14B104NA-BA20XCT

51-85128

48-ball FBGA

Commercial

CY14B104NA-BA20XC

51-85128

48-ball FBGA

CY14B104NA-BA20XIT

51-85128

48-ball FBGA

Industrial

CY14B104NA-BA20XI

51-85128

48-ball FBGA

CY14B104NA-ZSP20XCT

51-85160

54-pin TSOP II

Commercial

CY14B104NA-ZSP20XC

51-85160

54-pin TSOP II

CY14B104NA-ZSP20XIT

51-85160

54-pin TSOP II

Industrial

CY14B104NA-ZSP20XI

51-85160

54-pin TSOP II

25

CY14B104LA-ZS25XCT

51-85087

44-pin TSOP II

Commercial

CY14B104LA-ZS25XC

51-85087

44-pin TSOP II

CY14B104LA-ZS25XIT

51-85087

44-pin TSOP II

Industrial

CY14B104LA-ZS25XI

51-85087

44-pin TSOP II

CY14B104LA-BA25XCT

51-85128

48-ball FBGA

Commercial

CY14B104LA-BA25XC

51-85128

48-ball FBGA

CY14B104LA-BA25XIT

51-85128

48-ball FBGA

Industrial

CY14B104LA-BA25XI

51-85128

48-ball FBGA

CY14B104NA-ZS25XCT

51-85087

44-pin TSOP II

Commercial

CY14B104NA-ZS25XC

51-85087

44-pin TSOP II

CY14B104NA-ZS25XIT

51-85087

44-pin TSOP II

Industrial

CY14B104NA-ZS25XI

51-85087

44-pin TSOP II

CY14B104NA-BA25XCT

51-85128

48-ball FBGA

Commercial

CY14B104NA-BA25XC

51-85128

48-ball FBGA

CY14B104NA-BA25XIT

51-85128

48-ball FBGA

Industrial

CY14B104NA-BA25XI

51-85128

48-ball FBGA

CY14B104NA-BA25I

51-85128

48-ball FBGA

CY14B104NA-ZSP25XCT

51-85160

54-pin TSOP II

Commercial

CY14B104NA-ZSP25XC

51-85160

54-pin TSOP II

CY14B104NA-ZSP25XIT

51-85160

54-pin TSOP II

Industrial

CY14B104NA-ZSP25XI

51-85160

54-pin TSOP II

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Содержание CY14B104LA

Страница 1: ...volatile element in each memory cell The memory is organized as 512K bytes of 8 bits each or 256K words of 16 bits each The embedded nonvolatile elements incorporate QuantumTrap technology producing the world s most reliable nonvolatile memory The SRAM provides infinite read and write cycles while independent nonvolatile data resides in the highly reliable QuantumTrap cell Data transfers from the ...

Страница 2: ...expansion for 8 Mbit NC pin not connected to die 5 Address expansion for 16 Mbit NC pin not connected to die 6 HSB pin is not available in 44 TSOP II x16 package NC A8 NC NC VSS DQ6 DQ5 DQ4 VCC A13 DQ3 A12 DQ2 DQ1 DQ0 OE A9 CE NC A0 A1 A2 A3 A4 A5 A6 A11 A7 A14 A15 A16 A17 A18 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43...

Страница 3: ...e LOW Controls DQ15 DQ8 BLE Input Byte Low Enable Active LOW Controls DQ7 DQ0 VSS Ground Ground for the Device Must be connected to the ground of the system VCC Power Supply Power Supply Inputs to the Device HSB 6 Input Output Hardware Store Busy HSB When LOW this output indicates that a hardware store is in progress When pulled LOW external to the chip it initiates a nonvolatile STORE operation A...

Страница 4: ... QuantumTrap technology and is enabled by default on the CY14B104LA CY14B104NA During a normal operation the device draws current from VCC to charge a capacitor connected to the VCAP pin This stored charge is used by the chip to perform a single STORE operation If the voltage on the VCC pin drops below VSWITCH the part automatically disconnects the VCAP pin from VCC A STORE operation is initiated ...

Страница 5: ...he chip is disabled HSB is driven LOW It is important to use read cycles and not write cycles in the sequence although it is not necessary that OE be LOW for a valid sequence After the tSTORE cycle time is fulfilled the SRAM is activated again for the read and write operation Software RECALL Transfer the data from the nonvolatile memory to the SRAM with a software address sequence A software RECAL...

Страница 6: ...are must be issued to save the AutoStore state through subsequent power down cycles The part comes from the factory with AutoStore enabled Data Protection The CY14B104LA CY14B104NA protects data from corruption during low voltage conditions by inhibiting all externally initiated STORE and write operations The low voltage condition is detected when VCC VSWITCH If the CY14B104LA CY14B104NA is in a w...

Страница 7: ...pattern that is complex 4 byte pattern of 46 E6 49 53 hex or more random bytes as part of the final system manufac turing test to ensure these system routines work consistently Power up boot firmware routines should rewrite the nvSRAM into the desired state for example autostore enabled While the nvSRAM is shipped in a preset state best practice is to again rewrite the nvSRAM into the desired stat...

Страница 8: ...ustrial 70 70 52 mA mA mA ICC2 Average VCC Current during STORE All Inputs Don t Care VCC Max Average current for duration tSTORE 10 mA ICC3 9 AverageVCC Currentat tRC 200 ns 3V 25 C typical All I P cycling at CMOS levels Values obtained without output loads IOUT 0 mA 35 mA ICC4 Average VCAP Current during AutoStore Cycle All Inputs Don t Care VCC Max Average current for duration tSTORE 5 mA ISB V...

Страница 9: ...ut Capacitance TA 25 C f 1 MHz VCC 0 to 3 0V 7 pF COUT Output Capacitance 7 pF Thermal Resistance In the following table the thermal resistance parameters are listed 12 Parameter Description Test Conditions 48 FBGA 44 TSOP II 54 TSOP II Unit ΘJA Thermal Resistance Junction to Ambient Test conditions follow standard test methods and procedures for measuring thermal impedance in accordance with EIA ...

Страница 10: ... 0 0 ns tHZBE 12 Byte Disable to Output Inactive 8 10 15 ns SRAM Write Cycle tWC tWC Write Cycle Time 20 25 45 ns tPWE tWP Write Pulse Width 15 20 30 ns tSCE tCW Chip Enable To End of Write 15 20 30 ns tSD tDW Data Setup to End of Write 8 10 15 ns tHD tDH Data Hold After End of Write 0 0 0 ns tAW tAW Address Setup to End of Write 15 20 30 ns tSA tAS Address Setup to Start of Write 0 0 0 ns tHA tWR...

Страница 11: ...ddress Valid Address Data Output Output Data Valid Standby Active High Impedance CE OE BHE BLE ICC tHZCE tRC tACE tAA tLZCE tDOE tLZOE tDBE tLZBE tPU tPD tHZBE tHZOE Data Output Data Input Input Data Valid High Impedance Address Valid Address Previous Data tWC tSCE tHA tBW tAW tPWE tSA tSD tHD tHZWE tLZWE WE BHE BLE CE Note 18 CE or WE must be VIH during address transitions Feedback ...

Страница 12: ... Figure 10 SRAM Write Cycle 3 BHE and BLE Controlled 3 16 17 18 Data Output Data Input Input Data Valid High Impedance Address Valid Address tWC tSD tHD BHE BLE WE CE tSA tSCE tHA tBW tPWE Data Output Data Input Input Data Valid High Impedance Address Valid Address tWC tSD tHD BHE BLE WE CE tSCE tSA tBW tHA tAW tPWE Feedback ...

Страница 13: ...p RECALL 22 VSWITCH VHDIS VVCCRISE tSTORE tSTORE tHHHD tHHHD tDELAY tDELAY tLZHSB tLZHSB tHRECALL tHRECALL HSB OUT Autostore POWER UP RECALL Read Write Inhibited RWI POWER UP RECALL Read Write BROWN OUT Autostore POWER UP RECALL Read Write POWER DOWN Autostore Note20 Note20 Note23 Notes 19 tHRECALL starts from the time VCC rises above VSWITCH 20 If an SRAM write has not taken place since the last ...

Страница 14: ...0 30 ns tHA Address Hold Time 0 0 0 ns tRECALL RECALL Duration 200 200 200 μs Switching Waveforms Figure 12 CE and OE Controlled Software STORE RECALL Cycle 25 Figure 13 AutoStore Enable Disable Cycle W5 W5 W6 W W W6 W W W W W W W W6725 W5 W W 6 LJK PSHGDQFH GGUHVV GGUHVV GGUHVV 2 6 6725 RQO 4 7 5 W5 W5 W6 W W W6 W W W W W W W GGUHVV GGUHVV GGUHVV 2 4 7 5 W66 Notes 24 The software sequence is cloc...

Страница 15: ...Y tSTORE tHHHD tLZHSB Write latch set Write latch not set HSB IN HSB OUT DQ Data Out RWI HSB IN HSB OUT RWI HSB pin is driven high to VCC only by Internal SRAM is disabled as long as HSB IN is driven low HSB driver is disabled tDHSB 100kOhm resistor Address 1 Address 6 Address 1 Address 6 Soft Sequence Command tSS tSS CE Address VCC tSA tCW Soft Sequence Command tCW Notes 26 This is the amount of ...

Страница 16: ... CE WE OE BHE 3 BLE 3 Inputs Outputs 2 Mode Power H X X X X High Z Deselect Power down Standby L X X H H High Z Output Disabled Active L H L L L Data Out DQ0 DQ15 Read Active L H L H L Data Out DQ0 DQ7 DQ8 DQ15 in High Z Read Active L H L L H Data Out DQ8 DQ15 DQ0 DQ7 in High Z Read Active L H H L L High Z Output Disabled Active L H H H L High Z Output Disabled Active L H H L H High Z Output Disab...

Страница 17: ...OP II Commercial CY14B104NA ZSP20XC 51 85160 54 pin TSOP II CY14B104NA ZSP20XIT 51 85160 54 pin TSOP II Industrial CY14B104NA ZSP20XI 51 85160 54 pin TSOP II 25 CY14B104LA ZS25XCT 51 85087 44 pin TSOP II Commercial CY14B104LA ZS25XC 51 85087 44 pin TSOP II CY14B104LA ZS25XIT 51 85087 44 pin TSOP II Industrial CY14B104LA ZS25XI 51 85087 44 pin TSOP II CY14B104LA BA25XCT 51 85128 48 ball FBGA Commer...

Страница 18: ...087 44 pin TSOP II CY14B104NA ZS45XIT 51 85087 44 pin TSOP II Industrial CY14B104NA ZS45XI 51 85087 44 pin TSOP II CY14B104NA BA45XCT 51 85128 48 ball FBGA Commercial CY14B104NA BA45XC 51 85128 48 ball FBGA CY14B104NA BA45XIT 51 85128 48 ball FBGA Industrial CY14B104NA BA45XI 51 85128 48 ball FBGA CY14B104NA ZSP45XCT 51 85160 54 pin TSOP II Commercial CY14B104NA ZSP45XC 51 85160 54 pin TSOP II CY1...

Страница 19: ...s 25 25 ns Data Bus L x8 N x16 Density 104 4 Mb Voltage B 3 0V Cypress CY 14 B 104 L A ZS P 20 X C T NVSRAM 14 Auto Store Software Store Hardware Store Temperature C Commercial 0 to 70 C I Industrial 40 to 85 C Package BA 48 FBGA ZS TSOP II 45 45 ns X Pb Free Blank SnPb P 54 Pin Blank 44 Pin 48 Ball Die Revision Blank No Rev A 1st Rev Feedback ...

Страница 20: ...70 PLANE SEATING PIN 1 I D 44 1 18 517 0 729 0 800 BSC 0 5 0 400 0 016 0 300 0 012 EJECTOR PIN R G O K E A X S 11 735 0 462 10 058 0 396 10 262 0 404 1 194 0 047 0 991 0 039 0 150 0 0059 0 050 0 0020 0 0315 18 313 0 721 10 058 0 396 10 262 0 404 0 597 0 0235 0 406 0 0160 0 210 0 0083 0 120 0 0047 BASE PLANE 0 10 004 22 23 TOP VIEW BOTTOM VIEW 51 85087 A Feedback ...

Страница 21: ...age Diagrams continued A 1 A1 CORNER 0 75 0 75 Ø0 30 0 05 48X Ø0 25 M C A B Ø0 05 M C B A 0 15 4X 0 21 0 05 1 20 MAX C SEATING PLANE 0 53 0 05 0 25 C 0 15 C A1 CORNER TOP VIEW BOTTOM VIEW 2 3 4 3 75 5 25 B C D E F G H 6 5 4 6 5 2 3 1 D H F G E C B A 6 00 0 10 10 00 0 10 A 10 00 0 10 6 00 0 10 B 1 875 2 625 0 36 51 85128 D Feedback ...

Страница 22: ...PRELIMINARY CY14B104LA CY14B104NA Document 001 49918 Rev A Page 22 of 23 Figure 18 54 Pin TSOP II 51 85160 Package Diagrams continued 51 85160 Feedback ...

Страница 23: ...fication translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make...

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