Design Considerations
AN64846 - Getting Started with CapSense
®
Doc. No. 001-64846 Rev. *X
84
illustrates the schematic diagram with these recommendations. C1, C2, and C4 are decoupling capacitors
and C3 is the CMOD capacitor.
Figure 3-71. Example Schematics for Improved SNR
CY8CMBR3xxx
VCC
VDD
VSS
SCL
SDA
I2C
Connector
R1
R2
R3
R4
C2
C1
C4
CMOD
C3
shows an example board layout diagram with placements of decoupling and CMOD capacitors and routing
of ground and supply. (Note that the I
2
are not shown in the layout in this figure).
Figure 3-72. Example Board Layout for Improved SNR
A good CapSense schematics diagram must have all passive components shown in the schematics diagram.
The PCB layout shown above is for guidelines only. For a good layout, the inductance between multiple ground nodes
must be below 0.2 nH. The ground nodes are indicated in the schematics diagram in