Cypress Semiconductor Perform CY7C1511KV18 Скачать руководство пользователя страница 11

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CY7C1511KV18, CY7C1526KV18

CY7C1513KV18, CY7C1515KV18

Document Number: 001-00435 Rev. *E

Page 11 of 31

Write Cycle Descriptions

The write cycle description table for CY7C1511KV18 and CY7C1513KV18 follows.

[2, 10]

BWS

NWS

BWS

NWS

Comments

L–H

–

During the data portion of a write sequence

CY7C1511KV18

−

both nibbles (D

[7:0]

) are written into the device.

CY7C1513KV18

−

both bytes (D

[17:0]

) are written into the device.

–

L-H During the data portion of a write sequence

CY7C1511KV18

−

both nibbles (D

[7:0]

) are written into the device.

CY7C1513KV18

−

both bytes (D

[17:0]

) are written into the device.

L–H

–

During the data portion of a write sequence

CY7C1511KV18

−

only the lower nibble (D

[3:0]

) is written into the device, D

[7:4]

remains unaltered.

CY7C1513KV18

−

only the lower byte (D

[8:0]

) is written into the device, D

[17:9]

remains unaltered.

–

L–H During the data portion of a write sequence

CY7C1511KV18

−

only the lower nibble (D

[3:0]

) is written into the device, D

[7:4]

remains unaltered.

CY7C1513KV18

−

only the lower byte (D

[8:0]

) is written into the device, D

[17:9]

remains unaltered.

L–H

–

During the data portion of a write sequence

CY7C1511KV18

−

only the upper nibble (D

[7:4]

) is written into the device, D

[3:0]

remains unaltered.

CY7C1513KV18

−

only the upper byte (D

[17:9]

) is written into the device, D

[8:0]

remains unaltered.

–

L–H During the data portion of a write sequence

CY7C1511KV18

−

only the upper nibble (D

[7:4]

) is written into the device, D

[3:0]

remains unaltered.

CY7C1513KV18

−

only the upper byte (D

[17:9]

) is written into the device, D

[8:0]

remains unaltered.

L–H

–

No data is written into the devices during this portion of a write operation.

–

L–H No data is written into the devices during this portion of a write operation.

Write Cycle Descriptions

The write cycle description table for CY7C1526KV18 follows.

[2, 10]

BWS

L–H

–

During the data portion of a write sequence, the single byte (D

[8:0]

) is written into the device.

–

L–H

During the data portion of a write sequence, the single byte (D

[8:0]

) is written into the device.

L–H

–

No data is written into the device during this portion of a write operation.

–

L–H

No data is written into the device during this portion of a write operation.

Note

10. Is based on a write cycle that was initiated in accordance with the

Write Cycle Descriptions

table. NWS

, NWS

, BWS

and BWS

can be altered on

different portions of a write cycle, as long as the setup and hold requirements are achieved.

[+] Feedback

Содержание Perform CY7C1511KV18

Страница 1: ... 8V Synchronous Pipelined SRAMs equipped with QDR II architecture QDR II architecture consists of two separate ports the read port and the write port to access the memory array The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations QDR II architecture has separate data inputs and data outputs to completely elimin...

Страница 2: ...er Reg Reg Reg 16 21 32 8 NWS 1 0 VREF Write Add Decode Write Reg 16 A 20 0 21 8 CQ CQ DOFF Q 7 0 8 8 8 Write Reg Write Reg Write Reg C C 2M x 8 Array 2M x 8 Array 2M x 8 Array 8 CLK A 20 0 Gen K K Control Logic Address Register D 8 0 Read Add Decode Read Data Reg RPS WPS Control Logic Address Register Reg Reg Reg 18 21 36 9 BWS 0 VREF Write Add Decode Write Reg 18 A 20 0 21 9 CQ CQ DOFF Q 8 0 9 9...

Страница 3: ...S 1 0 VREF Write Add Decode Write Reg 36 A 19 0 20 18 CQ CQ DOFF Q 17 0 18 18 18 Write Reg Write Reg Write Reg C C 1M x 18 Array 1M x 18 Array 1M x 18 Array 1M x 18 Array 18 512K x 36 Array CLK A 18 0 Gen K K Control Logic Address Register D 35 0 Read Add Decode Read Data Reg RPS WPS Control Logic Address Register Reg Reg Reg 72 19 144 36 BWS 3 0 VREF Write Add Decode Write Reg 72 A 18 0 19 512K x...

Страница 4: ... Q6 D6 VDDQ VSS VSS VSS VDDQ NC NC Q0 M NC NC NC VSS VSS VSS VSS VSS NC NC D0 N NC D7 NC VSS A A A VSS NC NC NC P NC NC Q7 A A C A A NC NC NC R TDO TCK A A A C A A A TMS TDI CY7C1526KV18 8M x 9 1 2 3 4 5 6 7 8 9 10 11 A CQ A A WPS NC K NC 144M RPS A A CQ B NC NC NC A NC 288M K BWS0 A NC NC Q4 C NC NC NC VSS A NC A VSS NC NC D4 D NC D5 NC VSS VSS VSS VSS VSS NC NC NC E NC NC Q5 VDDQ VSS VSS VSS VDD...

Страница 5: ... A A NC D0 Q0 R TDO TCK A A A C A A A TMS TDI CY7C1515KV18 2M x 36 1 2 3 4 5 6 7 8 9 10 11 A CQ NC 288M A WPS BWS2 K BWS1 RPS A NC 144M CQ B Q27 Q18 D18 A BWS3 K BWS0 A D17 Q17 Q8 C D27 Q28 D19 VSS A NC A VSS D16 Q7 D8 D D28 D20 Q19 VSS VSS VSS VSS VSS Q16 D15 D7 E Q29 D29 Q20 VDDQ VSS VSS VSS VDDQ Q15 D6 Q6 F Q30 Q21 D21 VDDQ VDD VSS VDD VDDQ D14 Q14 Q5 G D30 D22 Q22 VDDQ VDD VSS VDD VDDQ Q13 D13...

Страница 6: ... CY7C1511KV18 8M x 9 4 arrays each of 2M x 9 for CY7C1526KV18 4M x 18 4 arrays each of 1M x 18 for CY7C1513KV18 and 2M x 36 4 arrays each of 512K x 36 for CY7C1515KV18 Therefore only 21 address inputs are needed to access the entire memory array of CY7C1511KV18 and CY7C1526KV18 20 address inputs for CY7C1513KV18 and 19 address inputs for CY7C1515KV18 These inputs are ignored when the appropriate p...

Страница 7: ...mpedance mode This pin cannot be connected directly to GND or left unconnected DOFF Input PLL Turn Off Active LOW Connecting this pin to ground turns off the PLL inside the device The timings in the PLL turned off operation differs from those listed in this data sheet For normal operation this pin is connected to a pull up through a 10 KΩ or less pull up resistor The device behaves in QDR I mode w...

Страница 8: ... The requested data is valid 0 45 ns from the rising edge of the output clock C or C or K or K when in single clock mode To maintain the internal logic each read access must be allowed to complete Each read access consists of four 18 bit data words and takes two clock cycles to complete Therefore read accesses to the device cannot be initiated on two consecutive K clock rises The internal logic of...

Страница 9: ... operations being initiated with the first access being a read Depth Expansion The CY7C1513KV18 has a port select input for each port This enables for easy depth expansion Both port selects are sampled on the rising edge of the positive input clock only K Each port select input can deselect the specified port Deselecting a port does not affect the other port All pending transactions read and write...

Страница 10: ... P S B W S ZQ CQ CQ Q K BUS MASTER CPU or ASIC DATA IN DATA OUT Address RPS WPS BWS Source K Source K Delayed K Delayed K CLKIN CLKIN Notes 2 X Don t Care H Logic HIGH L Logic LOW represents rising edge 3 Device powers up deselected with the outputs in a tristate condition 4 A represents address location latched by the devices when transaction was initiated A 1 A 2 and A 3 represents the address s...

Страница 11: ...7C1511KV18 only the upper nibble D 7 4 is written into the device D 3 0 remains unaltered CY7C1513KV18 only the upper byte D 17 9 is written into the device D 8 0 remains unaltered H L L H During the data portion of a write sequence CY7C1511KV18 only the upper nibble D 7 4 is written into the device D 3 0 remains unaltered CY7C1513KV18 only the upper byte D 17 9 is written into the device D 8 0 re...

Страница 12: ...ce only the byte D 17 9 is written into the device D 8 0 and D 35 18 remains unaltered H L H H L H During the data portion of a write sequence only the byte D 17 9 is written into the device D 8 0 and D 35 18 remains unaltered H H L H L H During the data portion of a write sequence only the byte D 26 18 is written into the device D 17 0 and D 35 27 remains unaltered H H L H L H During the data por...

Страница 13: ...the falling edge of TCK Instruction Register Three bit instructions are serially loaded into the instruction register This register is loaded when it is placed between the TDI and TDO pins as shown in TAP Controller Block Diagram on page 16 Upon power up the instruction register is loaded with the IDCODE instruction It is also loaded with the IDCODE instruction if the controller is placed in a res...

Страница 14: ...register After the data is captured it is possible to shift out the data by putting the TAP into the Shift DR state This places the boundary scan register between the TDI and TDO pins PRELOAD places an initial data pattern at the latched parallel outputs of the boundary scan register cells before the selection of another boundary scan test operation The shifting of data for the SAMPLE and PRELOAD ...

Страница 15: ...ontroller follows 11 TEST LOGIC RESET TEST LOGIC IDLE SELECT DR SCAN CAPTURE DR SHIFT DR EXIT1 DR PAUSE DR EXIT2 DR UPDATE DR 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 1 0 1 1 0 1 0 0 1 1 0 SELECT IR SCAN CAPTURE IR SHIFT IR EXIT1 IR PAUSE IR EXIT2 IR UPDATE IR Note 11 The 0 1 next to each state represents the value at TMS at the rising edge of TCK Feedback ...

Страница 16: ...ut HIGH Voltage 0 65VDD VDD 0 3 V VIL Input LOW Voltage 0 3 0 35VDD V IX Input and Output Load Current GND VI VDD 5 5 μA 0 0 1 2 29 30 31 Boundary Scan Register Identification Register 0 1 2 108 0 1 2 Instruction Register Bypass Register Selection Circuitry Selection Circuitry TAP Controller TDI TDO TCK TMS Notes 12 These characteristics pertain to the TAP inputs TMS TCK TDI and TDO Parallel load ...

Страница 17: ... tTDIH TDI Hold after Clock Rise 5 ns tCH Capture Hold after Clock Rise 5 ns Output Times tTDOV TCK Clock LOW to TDO Valid 10 ns tTDOX TCK Clock LOW to TDO Invalid 0 ns TAP Timing and Test Conditions Figure 2 shows the TAP timing and test conditions 16 Figure 2 TAP Timing and Test Conditions tTL tTH a TDO CL 20 pF Z0 50Ω GND 0 9V 50Ω 1 8V 0V ALL INPUT PULSES 0 9V Test Clock Test Mode Select TCK TM...

Страница 18: ... Instruction Codes Instruction Code Description EXTEST 000 Captures the input and output ring contents IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO This operation does not affect SRAM operation SAMPLE Z 010 Captures the input and output contents Places the boundary scan register between TDI and TDO Forces all SRAM output drivers to a High Z s...

Страница 19: ...2L 7 8P 35 10E 63 2A 91 3L 8 9R 36 10D 64 1A 92 1M 9 11P 37 9E 65 2B 93 1L 10 10P 38 10C 66 3B 94 3N 11 10N 39 11D 67 1C 95 3M 12 9P 40 9C 68 1B 96 1N 13 10M 41 9D 69 3D 97 2M 14 11N 42 11B 70 3C 98 3P 15 9M 43 11C 71 1D 99 2N 16 9N 44 9B 72 2C 100 2P 17 11L 45 10B 73 3E 101 1P 18 11M 46 11A 74 2D 102 3R 19 9L 47 10A 75 2E 103 4R 20 10L 48 9A 76 1E 104 4P 21 11K 49 8B 77 2F 105 5P 22 10K 50 7C 78 ...

Страница 20: ...and clock K K for 20 μs to lock the PLL PLL Constraints PLL uses K clock as its synchronizing input The input must have low phase jitter which is specified as tKC Var The PLL functions at frequencies down to 120 MHz If the input clock is unstable and the PLL is enabled then the PLL may lock onto an incorrect frequency causing unstable SRAM behavior To avoid this provide 20 μs of stable clock to re...

Страница 21: ...put HIGH Voltage Note 18 VDDQ 2 0 12 VDDQ 2 0 12 V VOL Output LOW Voltage Note 19 VDDQ 2 0 12 VDDQ 2 0 12 V VOH LOW Output HIGH Voltage IOH 0 1 mA Nominal Impedance VDDQ 0 2 VDDQ V VOL LOW Output LOW Voltage IOL 0 1 mA Nominal Impedance VSS 0 2 V VIH Input HIGH Voltage VREF 0 1 VDDQ 0 3 V VIL Input LOW Voltage 0 3 VREF 0 1 V IX Input Leakage Current GND VI VDDQ 5 5 μA IOZ Output Leakage Current GN...

Страница 22: ...atic 333 MHz x8 290 mA x9 290 x18 290 x36 290 300 MHz x8 280 mA x9 280 x18 280 x36 280 250 MHz x8 270 mA x9 270 x18 270 x36 270 200 MHz x8 250 mA x9 250 x18 250 x36 250 167 MHz x8 250 mA x9 250 x18 250 x36 250 AC Electrical Characteristics Over the Operating Range 13 Parameter Description Test Conditions Min Typ Max Unit VIH Input HIGH Voltage VREF 0 2 V VIL Input LOW Voltage VREF 0 2 V Electrical...

Страница 23: ...Test conditions follow standard test methods and procedures for measuring thermal impedance in accordance with EIA JESD51 13 7 C W ΘJC Thermal Resistance Junction to Case 3 73 C W Figure 4 AC Test Loads and Waveforms 1 25V 0 25V R 50Ω 5 pF INCLUDING JIG AND SCOPE ALL INPUT PULSES Device RL 50Ω Z0 50Ω VREF 0 75V VREF 0 75V 22 0 75V Under Test 0 75V Device Under Test OUTPUT 0 75V VREF VREF OUTPUT ZQ...

Страница 24: ...Rise 0 4 0 4 0 5 0 6 0 7 ns tSC tIVKH Control Setup to K Clock Rise RPS WPS 0 4 0 4 0 5 0 6 0 7 ns tSCDDR tIVKH Double Data Rate Control Setup to Clock K K Rise BWS0 BWS1 BWS2 BWS3 0 3 0 3 0 35 0 4 0 5 ns tSD tDVKH D X 0 Setup to Clock K K Rise 0 3 0 3 0 35 0 4 0 5 ns Hold Times tHA tKHAX Address Hold after K Clock Rise 0 4 0 4 0 5 0 6 0 7 ns tHC tKHIX Control Hold after K Clock Rise RPS WPS 0 4 0...

Страница 25: ...Z Clock C C Rise to High Z Active to High Z 26 27 0 45 0 45 0 45 0 45 0 50 ns tCLZ tCHQX1 Clock C C Rise to Low Z 26 27 0 45 0 45 0 45 0 45 0 50 ns PLL Timing tKC Var tKC Var Clock Phase Jitter 0 20 0 20 0 20 0 20 0 20 ns tKC lock tKC lock PLL Lock Time K C 20 20 20 20 20 μs tKC Reset tKC Reset K Static to PLL Reset 30 30 30 30 30 ns Switching Characteristics continued Over the Operating Range 22 ...

Страница 26: ...CLZ DOH tCHZ t t tKL tCYC tCCQO t CCQO tCQOH tCQOH KHKH KH Q00 Q03 Q01 Q02 Q20 Q23 Q21 Q22 tCO tCQDOH t tCQH tCQHCQH D10 D11 D12 D13 t SD tHD tSD tHD D30 D31 D32 D33 Notes 28 Q00 refers to output from address A0 Q01 refers to output from the next internal burst address following A0 that is A0 1 29 Outputs are disabled High Z one clock cycle after a NOP 30 In this example if address A2 A1 then data...

Страница 27: ...y 13 x 15 x 1 4 mm Commercial CY7C1526KV18 333BZC CY7C1513KV18 333BZC CY7C1515KV18 333BZC CY7C1511KV18 333BZXC 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free CY7C1526KV18 333BZXC CY7C1513KV18 333BZXC CY7C1515KV18 333BZXC CY7C1511KV18 333BZI 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Industrial CY7C1526KV18 333BZI CY7C1513KV18 333BZI CY7C1515KV18 333BZI CY7...

Страница 28: ...ray 13 x 15 x 1 4 mm Pb Free CY7C1526KV18 250BZXI CY7C1513KV18 250BZXI CY7C1515KV18 250BZXI 200 CY7C1511KV18 200BZC 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Commercial CY7C1526KV18 200BZC CY7C1513KV18 200BZC CY7C1515KV18 200BZC CY7C1511KV18 200BZXC 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free CY7C1526KV18 200BZXC CY7C1513KV18 200BZXC CY7C1515KV18 200BZ...

Страница 29: ...Array 13 x 15 x 1 4 mm Pb Free CY7C1526KV18 167BZXC CY7C1513KV18 167BZXC CY7C1515KV18 167BZXC CY7C1511KV18 167BZI 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Industrial CY7C1526KV18 167BZI CY7C1513KV18 167BZI CY7C1515KV18 167BZI CY7C1511KV18 167BZXI 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free CY7C1526KV18 167BZXI CY7C1513KV18 167BZXI CY7C1515KV18 167BZXI...

Страница 30: ... A B Ø0 05 M C B A 0 15 4X 0 35 0 06 SEATING PLANE 0 53 0 05 0 25 C 0 15 C PIN 1 CORNER TOP VIEW BOTTOM VIEW 2 3 4 5 6 7 8 9 10 10 00 14 00 B C D E F G H J K L M N 11 11 10 9 8 6 7 5 4 3 2 1 P R P R K M N L J H G F E D C B A A 15 00 0 10 13 00 0 10 B C 1 00 5 00 0 36 0 06 0 14 1 40 MAX SOLDER PAD TYPE NON SOLDER MASK DEFINED NSMD NOTES PACKAGE WEIGHT 0 475g JEDEC REFERENCE MO 216 DESIGN 4 6C PACKA...

Страница 31: ...ERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make changes without further notice to the materials described herein Cypress does not assume any liability arising out of the application or use of any product or circuit described herein Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may...

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