CY7C67300
Document #: 38-08015 Rev. *J
Page 86 of 99
SRAM Read Cycle
[15]
Notes
13. 0 wait state cycle.
14. t
AC
External SRAM access time = 12 ns for zero and one wait states. The External SRAM access time = 12 ns + (n – 1)*T for wait states = n, n > 1, T = 48 MHz
clock period.
15. Read timing is applicable for nXMEMSEL, nXRAMSEL, and nXROMSEL.
Table 137. SRAM Read Cycle Parameters
Parameter
Description
Min
Typical
Max
Unit
t
CR
CS LOW to RD LOW
1
ns
t
RDH
RD HIGH to Data Hold
0
ns
t
CDH
CS HIGH to Data Hold
0
ns
t
RPW
[13]
RD LOW Time
38
45
ns
t
AR
RD LOW to Address Valid
0
ns
t
AC
[14]
RAM Access to Data Valid
12
ns
Address
CS
RD
Din
t
AR
t
RPW
Data Valid
t
CR
t
AC
t
RDH
t
CDH
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