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CY8CKIT-062S2-43012 PSoC 62S2 Wi-Fi BT Pioneer Kit Guide, Doc. # 002-28109 Rev. *E
41
Hardware
3.2.6.3
WL/BT I/O Headers (J23)
These headers provide connectivity to a few of the CYW43012 GPIOs that are available at the cas-
tellated pads. All these I/O work at VDDIO_WL voltage (1.8 V by default).
Figure 3-10. I/O Headers
3.2.7
CapSense Circuit
A CapSense slider and two buttons, all supporting both self-capacitance (CSD) and mutual-
capacitance (CSX) sensing are connected to PSoC 6 MCU as
Figure 3-11
shows. Three external
capacitors - CMOD for CSD, CINTA and CINTB for CSX - are present on the CY8CMOD-062S2-
43012. Note that CINTA can be reused as CSH. For details on using CapSense including design
guidelines, see the
Getting Started with CapSense Design Guide
.
Figure 3-11. Schematics of CapSense Circuit
ARD_D0
ARD_D4
ARD_D3
ARD_D2
ARD_D1
ARD_D8
ARD_D7
ARD_D6
ARD_D5
ARD_D12
ARD_D11
ARD_D10
ARD_D9
ARD_D13
ARD_A1
ARD_A0
ARD_A5
ARD_A4
ARD_A3
ARD_A2
ARD_A7
ARD_A6
Arduino & Extended Headers
J2
CON 8x2
1
3
5
7
9
11
2
4
6
8
10
12
14
16
13
15
J3
CON10
1
2
3
4
5
6
7
8
9
10
J1
CON8
1
2
3
4
5
6
7
8
J4
CON8
1
2
3
4
5
6
7
8
P6_I2C_SCL
VREF
P6_I2C_SDA
VIN
XRES_L_MCU
VTARG
J1_5V0
J1_3V3
IO1
IO0
IO5
IO4
IO3
IO2
IO6
IO7
IO9
IO8
IO12
IO11
IO10
IO15
IO14
IO13
IO16
J23
CON 8x2
No Load
1
3
5
7
9
11
2
4
6
8
10
12
14
16
13
15
BT_UART_RXD
BT_UART_TXD
WL_UART_TX
WL_UART_RX
BT_UART_RTS
BT_UART_CTS
WL_GPIO_1
WL_GPIO_2
BT_I2S_DO
BT_GPIO_2
BT_I2S_CLK
BT_I2S_DI
BT_I2S_WS
BT_GPIO_5
BT_GPIO_4
BT_GPIO_3
A9
A8
USER_BTN_1
USER_BTN_2
J22
HEADER8
No Load
1
2
3
4
5
6
7
8
A12
A11
A10
A14
A13
A15
RGB_G_LED_L
R_LED_L
O_LED_L
RGB_B_LED_L
RGB_R_LED_L
J24
CON 3x2
No Load
1
2
3
4
5
6
J21
HEADER10
No Load
1
2
3
4
5
6
7
8
9
10
CapSense Buttons
CSB2
Tx
1
Rx
2
CSB1
Tx
1
Rx
2
CS_RX_TX
CS_BTN_1
CS_BTN_0
R173
0 OHM
No Load
HATCH
CapSense Shield
HATCH
CS_CAP_SH
CAP_SH1
SH
1
R56
0 OHM
CapSense Slider
CSS1
Slider
4
3
2
1
0
5
CS_SLD_0
CS_SLD_1
CS_SLD_2
CS_SLD_3
CS_SLD_4
CS_RX_TX
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