Cypress Semiconductor CY8CKIT-062-WiFi-BT, Руководство пользователя, Страница: 76 / 86

PSoC 6 WiFi-BT Pioneer Kit Guide, Doc. # 002-22677 Rev. *B 76
Configurations that can be changed, but will have adverse side-effects
Note: If you desire to change these configurations, contact Cypress technical support.
System Clocks
Name Configuration Used For Notes
Clk_Peri Divder = 1
Source clock for all
peripheral
The SDIO clock is always one-quarter of
Clk_Peri. Any change in the frequency of
Clk_Peri will reduce SDIO clock speed, thus
WiFi throughput. Communication with the
CY4343W radio will fail if the SDIO clock is
slower than 6 MHz.
Also the WICED API for UART, SPI, I2C,
PWM, CapSense, ADC, and so on, assume
that this clock is 100 MHz. So any changes will
cause unexpected behavior when using
WICED drivers.
Clk_Fast Divider = 1 Clock for CM4
Reducing the CM4 clock frequency reduces
WiFi throughput because the CM4 is unable to
process packets as fast
Clk_Hf[0]
Input: Clk_path_0
(FLL)
Divider: 1
Frequency: 100
MHz
Clocking CM4, CM0,
and Peripheral
Clk_Hf[0] is the root of Clk_Peri, Clk_Fast and
Clk_Slow. Any changes will reduce WiFi
throughput and cause WICED drivers to have
unexpected behavior
Clk_Hf[2]
Input: Clk_path_0
(FLL)
Divider: 2
Frequency: 50
MHz
Clock for SMIF (QSPI)
Any changes to this clock will cause the QSPI
to run slower
FLL
Input: IMO
Output: 100 MHz Clk_Hf[0] root and
Clk_Hf[2]
See Clk_Hf[0] and Clk_HF[2]