Cypress Semiconductor CY8C23433, Техническое описание

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CY8C23433, CY8C23533
Document Number: 001-44369 Rev. *B Page 30 of 37
AC Low Power Comparator Specifications
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40
°
C
≤
T
A
≤
85
°
C, or 3.0V to 3.6V and -40
°
C
≤
T
A
≤
85
°
C, respectively. Typical parameters apply to 5V and 3.3V at 25
°
C and
are for design guidance only.
AC Digital Block Specifications
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40
° C
≤
T
A
≤
85 ° C, or 3.0V to 3.6V and -40 ° C
≤
T
A
≤
85 ° C, respectively. Typical parameters apply to 5V and 3.3V at 25 ° C and
are for design guidance only.
Table 28. AC Low Power Comparator Specifications
Symbol Description Min Typ Max Units Notes
T
RLPC
LPC response time – – 50
μ
s
≥
50 mV overdrive comparator
reference set within V
REFLPC
Table 29. 5V and 3.3V AC Digital Block Specifications
Symbol Description Min Typ Max Units Notes
Timer Capture Pulse Width
50
[17] – – ns
Maximum Frequency, No Capture – – 49.2 MHz 4.75V < Vdd < 5.25V
Maximum Frequency, With Capture – – 24.6 MHz
Counter Enable Pulse Width
50
[17] – – ns
Maximum Frequency, No Enable Input – – 49.2 MHz 4.75V < Vdd < 5.25V
Maximum Frequency, Enable Input – – 24.6 MHz
Dead Band Kill Pulse Width:
Asynchronous Restart Mode 20 – – ns
Synchronous Restart Mode
50
[17] – – ns
Disable Mode
50
[17] – – ns
Maximum Frequency – – 49.2 MHz 4.75V < Vdd < 5.25V
CRCPRS
(PRS
Mode) Maximum Input Clock Frequency – – 49.2 MHz 4.75V < Vdd < 5.25V
CRCPRS
(CRC
Mode) Maximum Input Clock Frequency – – 24.6 MHz
SPIM Maximum Input Clock Frequency – – 8.2 MHz Maximum data rate at 4.1 MHz due
to 2 x over clocking.
SPIS Maximum Input Clock Frequency – – 4.1 MHz
Width of SS_ Negated Between
Transmissions
50
[17] – – ns
Transmitter Maximum Input Clock Frequency
Maximum Input Clock Frequency with Vdd
≥
4.75V, 2 Stop Bits
–
–
–
–
24.6
49.2
MHz
MHz
Maximum data rate at 3.08 M
Hz due
to
8 x over clocking
.
Maximum data rate at 6.15 MH
z due
to
8 x over clocking.
Receiver Maximum Input Clock Frequency
Maximum Input Clock Frequency with Vdd
≥
4.75V, 2 Stop Bits
–
–
–
–
24.6
49.2
MHz
MHz
Maximum data rate at 3.08 MH
z due
to
8 x over clocking.
Maximum data rate at 6.15 MHz
due
to
8 x over clocking.
Note
17. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
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