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CY7C1546V18, CY7C1557V18
CY7C1548V18, CY7C1550V18

Document Number: 001-06550 Rev. *E

Page 17 of 28

Identification Register Definitions

Instruction Field

Value

Description

CY7C1546V18

CY7C1557V18

CY7C1548V18

CY7C1550V18

Revision Number
(31:29)

000

Version number.

Cypress Device ID
(28:12)

11010111100000100 11010111100001100 11010111100010100 11010111100100100 Defines the type of

SRAM.

Cypress JEDEC ID
(11:1)

00000110100

Enables unique
identification of
SRAM vendor.

ID Register
Presence (0)

Indicates the
presence of an ID
register.

Scan Register Sizes

Register Name

Bit Size

Instruction

Bypass

Boundary Scan

109

Instruction Codes

Instruction

Code

Description

EXTEST

000

Captures the input and output ring contents.

IDCODE

001

Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operation.

SAMPLE Z

010

Captures the input and output contents. Places the boundary scan register between TDI and
TDO. Forces all SRAM output drivers to a High-Z state.

RESERVED

011

Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD

100

Captures the input and output ring contents. Places the boundary scan register between TDI
and TDO. Does not affect the SRAM operation.

RESERVED

101

Do Not Use: This instruction is reserved for future use.

RESERVED

110

Do Not Use: This instruction is reserved for future use.

BYPASS

111

Places the bypass register between TDI and TDO. This operation does not affect SRAM
operation.

[+] Feedback

Содержание CY7C1546V18

Страница 1: ...RAM equipped with DDR II architecture The DDR II consists of an SRAM core with advanced synchronous peripheral circuitry Addresses for read and write are latched on alternate rising edges of the input...

Страница 2: ...Data Reg R W DQ 7 0 Output Logic Reg Reg Reg 8 8 16 8 NWS 1 0 VREF Write Add Decode 8 8 LD Control 22 4M x 8 Array 4M x 8 Array Write Reg Write Reg CQ CQ R W DOFF QVLD 8 CLK A 21 0 Gen K K Control Lo...

Страница 3: ...R W DQ 17 0 Output Logic Reg Reg Reg 18 18 36 18 BWS 1 0 VREF Write Add Decode 18 18 LD Control 21 2M x 18 Array 2M x 18 Array Write Reg Write Reg CQ CQ R W DOFF QVLD 18 CLK A 19 0 Gen K K Control Log...

Страница 4: ...SS VSS VDDQ NC NC DQ0 M NC NC NC VSS VSS VSS VSS VSS NC NC NC N NC NC NC VSS A A A VSS NC NC NC P NC NC DQ7 A A QVLD A A NC NC NC R TDO TCK A A A NC A A A TMS TDI CY7C1557V18 8M x 9 1 2 3 4 5 6 7 8 9...

Страница 5: ...NC NC DQ0 R TDO TCK A A A NC A A A TMS TDI CY7C1550V18 2M x 36 1 2 3 4 5 6 7 8 9 10 11 A CQ NC 144M A R W BWS2 K BWS1 LD A A CQ B NC DQ27 DQ18 A BWS3 K BWS0 A NC NC DQ8 C NC NC DQ28 VSS A NC A VSS NC...

Страница 6: ...Y7C1548V18 BWS0 controls D 8 0 and BWS1 controls D 17 9 CY7C1550V18 BWS0 controls D 8 0 BWS1 controls D 17 9 BWS2 controls D 26 18 and BWS3 controls D 35 27 All the Byte Write Selects are sampled on t...

Страница 7: ...ugh a 10 Kohm or less pull up resistor The device behaves in DDR I mode when the DLL is turned off In this mode the device is operated at a frequency of up to 167 MHz with DDR I timing TDO Output TDO...

Страница 8: ...ter provided BWS 1 0 are both asserted active The 36 bits of data are then written into the memory array at the specified location Write accesses can be initiated on every rising edge of the positive...

Страница 9: ...rives DLL These chips use a Delay Lock Loop DLL that is designed to function between 120 MHz and the specified maximum clock frequency The DLL may be disabled by applying ground to the DOFF pin When t...

Страница 10: ...548V18 only the lower byte D 8 0 is written into the device D 17 9 remains unaltered H L L H During the data portion of a write sequence CY7C1546V18 only the upper nibble D 7 4 is written into the dev...

Страница 11: ...nto the device D 35 9 remains unaltered L H H H L H During the data portion of a write sequence only the lower byte D 8 0 is written into the device D 35 9 remains unaltered H L H H L H During the dat...

Страница 12: ...edge of TCK Instruction Register Three bit instructions can be serially loaded into the instruction register This register is loaded when it is placed between the TDI and TDO pins as shown in TAP Cont...

Страница 13: ...an register Once the data is captured it is possible to shift out the data by putting the TAP into the Shift DR state This places the boundary scan register between the TDI and TDO pins PRELOAD places...

Страница 14: ...er follows 10 TEST LOGIC RESET TEST LOGIC IDLE SELECT DR SCAN CAPTURE DR SHIFT DR EXIT1 DR PAUSE DR EXIT2 DR UPDATE DR 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 1 0 1 1 0 1 0 0 1 1 0 SELECT IR SCAN CA...

Страница 15: ...VIH Input HIGH Voltage 0 65VDD VDD 0 3 V VIL Input LOW Voltage 0 3 0 35VDD V IX Input and Output Load Current GND VI VDD 5 5 A 0 0 1 2 29 30 31 Boundary Scan Register Identification Register 0 1 2 10...

Страница 16: ...Rise 5 ns Hold Times tTMSH TMS Hold after TCK Clock Rise 5 ns tTDIH TDI Hold after Clock Rise 5 ns tCH Capture Hold after Clock Rise 5 ns Output Times tTDOV TCK Clock LOW to TDO Valid 10 ns tTDOX TCK...

Страница 17: ...ion Codes Instruction Code Description EXTEST 000 Captures the input and output ring contents IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO This...

Страница 18: ...3A 90 2L 7 8P 35 10E 63 2A 91 3L 8 9R 36 10D 64 1A 92 1M 9 11P 37 9E 65 2B 93 1L 10 10P 38 10C 66 3B 94 3N 11 10N 39 11D 67 1C 95 3M 12 9P 40 9C 68 1B 96 1N 13 10M 41 9D 69 3D 97 2M 14 11N 42 11B 70 3...

Страница 19: ...e power and clock K K for 2048 cycles to lock the DLL DLL Constraints DLL uses K clock as its synchronizing input The input must have low phase jitter which is specified as tKC Var The DLL functions a...

Страница 20: ...put LOW Voltage Note 18 VDDQ 2 0 12 VDDQ 2 0 12 V VOH LOW Output HIGH Voltage IOH 0 1 mA Nominal Impedance VDDQ 0 2 VDDQ V VOL LOW Output LOW Voltage IOL 0 1 mA Nominal Impedance VSS 0 2 V VIH Input H...

Страница 21: ...r process change that may affect these parameters Parameter Description Test Conditions Max Unit CIN Input Capacitance TA 25 C f 1 MHz VDD 1 8V VDDQ 1 5V 5 5 pF CCLK Clock Input Capacitance 8 5 pF CO...

Страница 22: ...VREF 0 75V VREF 0 75V 21 0 75V Under Test 0 75V Device Under Test OUTPUT 0 75V VREF VREF OUTPUT ZQ ZQ a Slew Rate 2 V ns RQ 250 b RQ 250 Note 21 Unless otherwise noted test conditions assume signal tr...

Страница 23: ...0 2 ns tCQDOH tCQHQX Echo Clock High to Data Invalid 0 2 0 2 0 2 ns tCQH tCQHCQL Output Clock CQ CQ HIGH 24 0 88 1 03 1 15 ns tCQHCQH tCQHCQH CQ Clock Rise to CQ Clock Rise 24 rising edge to rising e...

Страница 24: ...D t CLZ t CHZ D20 D21 D30 D31 t CQDOH Q00 Q11 Q01 Q10 tDOH tCO Q40 Q41 tCQD t t tCQH CQHCQH Notes 29 Q00 refers to output from address A0 Q01 refers to output from the next internal burst address foll...

Страница 25: ...Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Industrial CY7C1557V18 375BZI CY7C1548V18 375BZI CY7C1550V18 375BZI CY7C1546V18 375BZXI 51 85195 165 Ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Pb Fr...

Страница 26: ...18 300BZXC CY7C1546V18 300BZI 51 85195 165 Ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Industrial CY7C1557V18 300BZI CY7C1548V18 300BZI CY7C1550V18 300BZI CY7C1546V18 300BZXI 51 85195 165 Ball Fi...

Страница 27: ...V18 CY7C1550V18 Document Number 001 06550 Rev E Page 27 of 28 Package Diagram Figure 6 165 Ball FBGA 15 x 17 x 1 4 mm 0 2 2 8 8 8 3 4 0 0 2 2 4 0 6 7 44 6 7 0 2 0 2 3 2 0 490 3 2 3 3 4 3 0 7 4 G 2 2 3...

Страница 28: ...IND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make chang...

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