CY7C1510KV18, CY7C1525KV18
CY7C1512KV18, CY7C1514KV18
Document Number: 001-00436 Rev. *E
Page 24 of 30
Output Times
t
CO
t
CHQV
C/C Clock Rise (or K/K in single
clock mode) to Data Valid
–
0.45
–
0.45
–
0.45
–
0.45
–
0.50
ns
t
DOH
t
CHQX
Data Output Hold after Output C/C
Clock Rise (Active to Active)
–0.45
–
–0.45
–
–0.45
–
–0.45
–
–0.50
–
ns
t
CCQO
t
CHCQV
C/C Clock Rise to Echo Clock Valid
–
0.45
–
0.45
–
0.45
–
0.45
–
0.50
ns
t
CQOH
t
CHCQX
Echo Clock Hold after C/C Clock
Rise
–0.45
–
–0.45
–
–0.45
–
–0.45
–
–0.50
–
ns
t
CQD
t
CQHQV
Echo Clock High to Data Valid
0.25
0.27
–
0.30
–
0.35
–
0.40
ns
t
CQDOH
t
CQHQX
Echo Clock High to Data Invalid
–0.25
–
–0.27
–
–0.30
–
–0.35
–
–0.40
–
ns
t
CQH
t
CQHCQL
Output Clock (CQ/CQ) HIGH
[23]
1.25
–
1.40
–
1.75
–
2.25
–
2.75
–
ns
t
CQHCQH
t
CQHCQH
CQ Clock Rise to CQ Clock Rise
(rising edge to rising edge)
[23]
1.25
–
1.40
–
1.75
–
2.25
–
2.75
–
ns
t
CHZ
t
CHQZ
Clock (C/C) Rise to High-Z
(Active to High-Z)
[24, 25]
–
0.45
–
0.45
–
0.45
–
0.45
–
0.50
ns
t
CLZ
t
CHQX1
Clock (C/C) Rise to Low-Z
[24, 25]
–0.45
–
–0.45
–
–0.45
–
–0.45
–
–0.50
–
ns
PLL Timing
t
KC Var
t
KC Var
Clock Phase Jitter
–
0.20
–
0.20
–
0.20
–
0.20
–
0.20
ns
t
KC lock
t
KC lock
PLL Lock Time (K, C)
20
–
20
–
20
–
20
–
20
–
μ
s
t
KC Reset
t
KC Reset
K Static to PLL Reset
30
30
30
30
30
ns
Switching Characteristics
(continued)
Over the Operating Range
[20, 21]
Cypress
Parameter
Consortium
Parameter
Description
333 MHz
300 MHz
250 MHz
200 MHz
167 MHz
Unit
Min Max Min Max Min Max Min Max Min Max
Notes
23. These parameters are extrapolated from the input timing parameters (t
CYC
/2
- 250 ps, where 250 ps is the internal jitter). These parameters are only guaranteed by
design and are not tested in production.
24. t
CHZ
, t
CLZ
, are specified with a load capacitance of 5 pF as in part (b) of
AC Test Loads and Waveforms
. Transition is measured
±
100 mV from steady state voltage.
25. At any voltage and temperature t
CHZ
is less than t
CLZ
and t
CHZ
less than t
CO
.
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