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CY7C1416AV18, CY7C1427AV18
CY7C1418AV18, CY7C1420AV18

Document Number: 38-05616 Rev. *F

Page 18 of 31

Boundary Scan Order 

Bit #

Bump ID

Bit #

Bump ID

Bit #

Bump ID

Bit #

Bump ID

0

6R

28

10G 56

6A

84

1J

1

6P

29

9G

57

5B

85

2J

2

6N

30

11F

58

5A

86

3K

3

7P

31

11G

59

4A

87

3J

4

7N

32

9F

60

5C

88

2K

5

7R

33

10F

61

4B

89

1K

6

8R

34

11E

62

3A

90

2L

7

8P

35

10E

63

2A

91

3L

8

9R

36

10D

64

1A

92

1M

9

11P

37

9E

65

2B

93

1L

10

10P

38

10C

66

3B

94

3N

11

10N

39

11D

67

1C

95

3M

12

9P

40

9C

68

1B

96

1N

13

10M

41

9D

69

3D

97

2M

14

11N

42

11B

70

3C

98

3P

15

9M

43

11C

71

1D

99

2N

16

9N

44

9B

72

2C

100

2P

17

11L

45

10B

73

3E

101

1P

18

11M

46

11A

74

2D

102

3R

19

9L

47

10A

75

2E

103

4R

20

10L

48

9A

76

1E

104

4P

21

11K

49

8B

77

2F

105

5P

22

10K

50

7C

78

3F

106

5N

23

9J

51

6C

79

1G

107

5R

24

9K

52

8A

80

1F

108

Internal

25

10J

53

7A

81

3G

26

11J

54

7B

82

2G

27

11H

55

6B

83

1H

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Содержание CY7C1416AV18

Страница 1: ...es of the input K clock Write data is registered on the rising edges of both K and K Read data is driven on the rising edges of C and C if provided or on the rising edge of K and K if C C are not prov...

Страница 2: ...egister Read Add Decode Read Data Reg R W Output Logic Reg Reg Reg 8 16 8 NWS 1 0 VREF Write Add Decode 8 21 C C 8 LD Control R W DOFF 2M x 8 Array 2M x 8 Array 8 DQ 7 0 8 CQ CQ Write Reg Write Reg CL...

Страница 3: ...R W Output Logic Reg Reg Reg 18 36 18 BWS 1 0 VREF Write Add Decode 18 21 C C 18 LD Control Burst Logic A0 A 20 1 R W DOFF 1M x 18 Array 1M x 18 Array 20 18 DQ 17 0 18 CQ CQ Write Reg Write Reg CLK A...

Страница 4: ...DDQ VSS VSS VSS VDDQ NC NC DQ0 M NC NC NC VSS VSS VSS VSS VSS NC NC NC N NC NC NC VSS A A A VSS NC NC NC P NC NC DQ7 A A C A A NC NC NC R TDO TCK A A A C A A A TMS TDI CY7C1427AV18 4M x 9 1 2 3 4 5 6...

Страница 5: ...A A NC NC DQ0 R TDO TCK A A A C A A A TMS TDI CY7C1420AV18 1M x 36 1 2 3 4 5 6 7 8 9 10 11 A CQ NC 144M A R W BWS2 K BWS1 LD A NC 72M CQ B NC DQ27 DQ18 A BWS3 K BWS0 A NC NC DQ8 C NC NC DQ28 VSS A A0...

Страница 6: ...A0 Input Synchronous Address Inputs These address inputs are multiplexed for both read and write operations Internally the device is organized as 4M x 8 2 arrays each of 2M x 8 for CY7C1416AV18 4M x...

Страница 7: ...ed between ZQ and ground Alternatively connect this pin directly to VDDQ which enables the minimum impedance mode This pin cannot be connected directly to GND or left unconnected DOFF Input DLL Turn O...

Страница 8: ...the address in a linear fashion On the following K clock rise the data presented to D 17 0 is latched and stored into the 18 bit write data register provided BWS 1 0 are both asserted active On the s...

Страница 9: ...to the output clock of the DDR II In the single clock mode CQ is generated with respect to K and CQ is generated with respect to K The timings for the echo clocks is shown in the AC Timing Table DLL T...

Страница 10: ...yte D 8 0 is written into the device D 17 9 remains unaltered H L L H During the data portion of a write sequence CY7C1416AV18 only the upper nibble D 7 4 is written into the device D 3 0 remains unal...

Страница 11: ...ten into the device D 35 9 remains unaltered L H H H L H During the Data portion of a write sequence only the lower byte D 8 0 is written into the device D 35 9 remains unaltered H L H H L H During th...

Страница 12: ...ing edge of TCK Instruction Register Three bit instructions can be serially loaded into the instruction register This register is loaded when it is placed between the TDI and TDO pins as shown in TAP...

Страница 13: ...ary scan register After the data is captured it is possible to shift out the data by putting the TAP into the Shift DR state This places the boundary scan register between the TDI and TDO pins PRELOAD...

Страница 14: ...ontroller follows 9 TEST LOGIC RESET TEST LOGIC IDLE SELECT DR SCAN CAPTURE DR SHIFT DR EXIT1 DR PAUSE DR EXIT2 DR UPDATE DR 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 1 0 1 1 0 1 0 0 1 1 0 SELECT IR S...

Страница 15: ...HIGH Voltage 0 65VDD VDD 0 3 V VIL Input LOW Voltage 0 3 0 35VDD V IX Input and Output Load Current GND VI VDD 5 5 A 0 0 1 2 29 30 31 Boundary Scan Register Identification Register 0 1 2 108 0 1 2 In...

Страница 16: ...tTDIH TDI Hold after Clock Rise 5 ns tCH Capture Hold after Clock Rise 5 ns Output Times tTDOV TCK Clock LOW to TDO Valid 10 ns tTDOX TCK Clock LOW to TDO Invalid 0 ns TAP Timing and Test Conditions F...

Страница 17: ...nstruction Codes Instruction Code Description EXTEST 000 Captures the input and output ring contents IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TD...

Страница 18: ...7 8P 35 10E 63 2A 91 3L 8 9R 36 10D 64 1A 92 1M 9 11P 37 9E 65 2B 93 1L 10 10P 38 10C 66 3B 94 3N 11 10N 39 11D 67 1C 95 3M 12 9P 40 9C 68 1B 96 1N 13 10M 41 9D 69 3D 97 2M 14 11N 42 11B 70 3C 98 3P...

Страница 19: ...ock K K for 1024 cycles to lock the DLL DLL Constraints DLL uses K clock as its synchronizing input The input must have low phase jitter which is specified as tKC Var The DLL functions at frequencies...

Страница 20: ...V VOH Output HIGH Voltage Note 16 VDDQ 2 0 12 VDDQ 2 0 12 V VOL Output LOW Voltage Note 17 VDDQ 2 0 12 VDDQ 2 0 12 V VOH LOW Output HIGH Voltage IOH 0 1 mA Nominal Impedance VDDQ 0 2 VDDQ V VOL LOW O...

Страница 21: ...atic 300MHz x8 345 mA x9 345 x18 360 x36 400 278MHz x8 325 mA x9 330 x18 345 x36 370 250MHz x8 320 mA x9 320 x18 330 x36 350 200MHz x8 300 mA x9 300 x18 300 x36 315 167MHz x8 285 mA x9 285 x18 290 x36...

Страница 22: ...e Junction to Ambient Test conditions follow standard test methods and procedures for measuring thermal impedance in accordance with EIA JESD51 17 2 C W JC Thermal Resistance Junction to Case 3 2 C W...

Страница 23: ...up to K Clock Rise LD R W 0 4 0 4 0 5 0 6 0 7 ns tSCDDR tIVKH Double Data Rate Control Setup to Clock K K Rise BWS0 BWS1 BWS2 BWS3 0 3 0 3 0 35 0 4 0 5 ns tSD 23 tDVKH D X 0 Setup to Clock K K Rise 0...

Страница 24: ...CHQZ Clock C C Rise to High Z Active to High Z 24 25 0 45 0 45 0 45 0 45 0 50 ns tCLZ tCHQX1 Clock C C Rise to Low Z 24 25 0 4 5 0 4 5 0 4 5 0 4 5 0 5 0 ns DLL Timing tKC Var tKC Var Clock Phase Jitte...

Страница 25: ...tKH tKHKH tKL tCYC A0 D20 D21 D30 D31 Q00 Q11 Q01 Q10 A1 A2 A3 A4 Q41 tCCQO tCQOH tCCQO tCQOH tKL tCYC K K LD R W A DQ C C CQ CQ SA tKH tKHKH tCQD tCQDOH Notes 26 Q00 refers to output from address A0...

Страница 26: ...ll Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Industrial CY7C1427AV18 300BZI CY7C1418AV18 300BZI CY7C1420AV18 300BZI CY7C1416AV18 300BZXI 51 85195 165 Ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm...

Страница 27: ...18 250BZXI 200 CY7C1416AV18 200BZC 51 85195 165 Ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Commercial CY7C1427AV18 200BZC CY7C1418AV18 200BZC CY7C1420AV18 200BZC CY7C1416AV18 200BZXC 51 85195 16...

Страница 28: ...AV18 167BZXC CY7C1416AV18 167BZI 51 85195 165 Ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Industrial CY7C1427AV18 167BZI CY7C1418AV18 167BZI CY7C1420AV18 167BZI CY7C1416AV18 167BZXI 51 85195 165...

Страница 29: ...8AV18 CY7C1420AV18 Document Number 38 05616 Rev F Page 29 of 31 Package Diagram Figure 6 165 ball FBGA 15 x 17 x 1 4 mm 51 85195 0 2 2 8 8 8 3 4 0 0 2 2 4 0 6 7 44 6 7 0 2 0 2 3 2 0 490 3 2 3 3 4 3 0...

Страница 30: ...h First Street to 198 Champion Court Added Power up sequence and Wave form on page 19 Added Footnotes 13 14 15 on page 19 Replaced Three state with Tri state Changed the description of IX from Input L...

Страница 31: ...ed above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO T...

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