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CY7C1381D, CY7C1381F

CY7C1383D, CY7C1383F

Document #: 38-05544 Rev. *F

Page 29 of 29

Document History Page

Document Title: CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM

Document Number: 38-05544

REV.

ECN NO. Issue Date

Orig. of

Change

Description of Change

254518

See ECN

RKF

New data sheet

288531

See ECN

SYT

Edited description under “IEEE 1149.1 Serial Boundary Scan (JTAG)” for

non-compliance with 1149.1

Removed 117-MHz Speed Bin

Added Pb-free information for 100-Pin TQFP, 119 BGA and 165 FBGA

package

Added comment of ‘Pb-free BG packages availability’ below the Ordering Infor-

mation

326078

See ECN

PCI

Address expansion pins/balls in the pinouts for all packages are modified as

per JEDEC standard

Added description on EXTEST Output Bus Tri-State

Changed description on the Tap Instruction Set Overview and Extest

Changed Device Width (23:18) for 119-BGA from 000001 to 101001

Added separate row for 165 -FBGA Device Width (23:18)

Changed

and

for TQFP Package

from 31 and 6

C/W to 28.66 and

4.08

C/W respectively

Changed

and

for BGA Package

from 45 and 7

C/W to 23.8 and 6.2

C/W respectively

Changed

and

for FBGA Package

from 46 and 3

C/W to 20.7 and 4.0

C/W respectively

Modified V

OL,

test conditions

Removed comment of ‘Pb-free BG packages availability’ below the Ordering

Information

Updated Ordering Information Table

Changed from Preliminary to Final

351895

See ECN

PCI

Updated Ordering Information Table

416321

See ECN

NXR

Changed address of Cypress Semiconductor Corporation on Page# 1 from

“3901 North First Street” to “198 Champion Court”

Changed the description of I

from Input Load Current to Input Leakage

Current on page# 18

Changed the I

current values of MODE on page # 18 from –5

A and 30

to –30

A and 5

Changed the I

current values of ZZ on page # 18 from –30

A and 5

to –5

A and 30

Changed V

< V

to V

< V

on page # 18

Replaced Package Name column with Package Diagram in the Ordering

Information table

Updated Ordering Information Table

475009

See ECN

VKN

Added the Maximum Rating for Supply Voltage on V

DDQ

Relative to GND

Changed t

, t

from 25 ns to 20 ns and t

TDOV

from 5 ns to 10 ns in TAP AC

Switching Characteristics table.

Updated the Ordering Information table.

776456

See ECN

VKN

Added Part numbers CY7C1381F and CY7C1383F and its related information

Added footnote# 3 regarding Chip Enable

Updated Ordering Information table

[+] Feedback

Содержание CY7C1381D

Страница 1: ...y a positive edge triggered clock input CLK The synchronous inputs include all addresses all data inputs address pipelining chip enable CE1 depth expansion chip enables CE2 and CE3 2 burst control inp...

Страница 2: ...E CE1 CE2 CE3 OE GW SLEEP DQA DQP A BYTE WRITE REGISTER DQB DQP B WRITE REGISTER DQC DQP C WRITE REGISTER BYTE WRITE REGISTER DQD DQP D BYTE WRITE REGISTER DQD DQP D BYTE WRITE REGISTER DQC DQP C WRIT...

Страница 3: ...5 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 MODE CY7C1381D 512K x 36 VSS DNU A A A A A 1 A 0 NC NC V SS V DD A A A A A A A A A NC NC VDDQ V...

Страница 4: ...VDD DQD DQD DQD DQD ADSC NC CE1 OE ADV GW VSS VSS VSS VSS VSS VSS VSS VSS DQPA MODE DQPD DQPB BWB BWC NC VDD NC BWA NC BWE BWD ZZ 2 3 4 5 6 7 1 A B C D E F G H J K L M N P R T U VDDQ NC 288M NC 144M...

Страница 5: ...DQB DQB NC DQB NC DQA DQA VDD VDDQ VDD VDDQ DQB VDD NC VDD DQA VDD VDDQ DQA VDDQ VDD VDD VDDQ VDD VDDQ DQA VDDQ A A VSS A A A DQB DQB DQB ZZ DQA DQA DQPA DQA A VDDQ A CY7C1383D 1M x 18 A0 A VSS 2 3 4...

Страница 6: ...m a deselected state ADV Input Synchronous Advance input signal Sampled on the rising edge of CLK When asserted it automatically increments the address in a burst cycle ADSP Input Synchronous Address...

Страница 7: ...initiated when the following conditions are satisfied at clock rise 1 CE1 CE2 CE3 2 are all asserted active and 2 ADSP is asserted LOW The addresses presented are loaded into the address register and...

Страница 8: ...can follow either a linear or interleaved burst order The burst order is determined by the state of the MODE input A LOW on MODE will select a linear burst sequence A HIGH on MODE will select an inte...

Страница 9: ...H D Write Cycle Continue Burst Next H X X L X H L L X L H D Read Cycle Suspend Burst Current X X X L H H H H L L H Q Read Cycle Suspend Burst Current X X X L H H H H H L H Tri State Read Cycle Suspen...

Страница 10: ...D A DQD DQA DQPD DQPA H L L H H L Write Bytes D B DQD DQA DQPD DQPA H L L H L H Write Bytes D B A DQD DQB DQA DQPD DQPB DQPA H L L H L L Write Bytes D B DQD DQB DQPD DQPB H L L L H H Write Bytes D B A...

Страница 11: ...MSB of any register See TAP Controller Block Diagram Test Data Out TDO The TDO output ball is used to serially clock data out from the registers The output is active depending upon the current state...

Страница 12: ...aded into the instruction register upon power up or whenever the TAP controller is given a test logic reset state SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected be...

Страница 13: ...ed but are reserved for future use Do not use these instructions TAP Timing TAP AC Switching Characteristics Over the Operating Range 10 11 Parameter Description Min Max Unit Clock tTCYC TCK Clock Cyc...

Страница 14: ...uivalent TDO 1 5V 20pF Z 50 O 50 TDO 1 25V 20pF Z 50 O 50 TAP DC Electrical Characteristics And Operating Conditions 0 C TA 70 C VDD 3 3V 0 165V unless otherwise noted 12 Parameter Description Conditi...

Страница 15: ...can Order 165 ball fBGA package 89 89 Identification Codes Instruction Code Description EXTEST 000 Captures Input Output ring contents Places the boundary scan register between TDI and TDO Forces all...

Страница 16: ...L5 28 E6 50 B3 72 L2 7 R6 29 D6 51 A3 73 N2 8 U6 30 C7 52 C2 74 P2 9 R7 31 B7 53 A2 75 R3 10 T7 32 C6 54 B1 76 T1 11 P6 33 A6 55 C1 77 R1 12 N7 34 C5 56 D2 78 T2 13 M6 35 B5 57 E1 79 L3 14 L7 36 G5 5...

Страница 17: ...H3 8 P9 38 B9 68 J1 9 P10 39 C10 69 K1 10 R10 40 A8 70 L1 11 R11 41 B8 71 M1 12 H11 42 A7 72 J2 13 N11 43 B7 73 K2 14 M11 44 B6 74 L2 15 L11 45 A6 75 M2 16 K11 46 B5 76 N1 17 J11 47 A5 77 N2 18 M10 48...

Страница 18: ...ge 17 for 3 3V IO 2 0 VDD 0 3V V for 2 5V IO 1 7 VDD 0 3V V VIL Input LOW Voltage 17 for 3 3V IO 0 3 0 8 V for 2 5V IO 0 3 0 7 V IX Input Leakage Current except ZZ and MODE GND VI VDDQ 5 5 A Input Cur...

Страница 19: ...ce Junction to Ambient Test conditions follow standard test methods and procedures for measuring thermal impedance in accordance with EIA JESD51 28 66 23 8 20 7 C W JC Thermal Resistance Junction to C...

Страница 20: ...5 0 5 ns tADH ADSP ADSC Hold After CLK Rise 0 5 0 5 ns tWEH GW BWE BW A D Hold After CLK Rise 0 5 0 5 ns tADVH ADV Hold After CLK Rise 0 5 0 5 ns tDH Data Input Hold After CLK Rise 0 5 0 5 ns tCEH Ch...

Страница 21: ...DV tOEHZ tCDV SingleREAD BURST READ tOEV tOELZ tCHZ Burstwrapsaround toitsinitialstate t ADVH t ADVS t WEH t WES tADH tADS Q A2 Q A2 1 Q A2 2 Q A1 Q A2 Q A2 1 Q A2 2 Q A2 3 A2 ADVsuspendsburst Deselec...

Страница 22: ...D A1 D A3 D A3 1 D A3 2 D A2 3 A2 A3 Extended BURST WRITE D A2 2 Single WRITE tADH tADS tADH tADS t OEHZ tADVH tADVS tWEH tWES t DH t DS t WEH t WES Byte write signals are ignored for rst cycle when...

Страница 23: ...CES Single WRITE D A3 A3 A4 BURST READ Back to Back READs High Z Q A2 Q A4 Q A4 1 Q A4 2 Q A4 3 t WEH t WES t OEHZ tDH tDS tCDV tOELZ A1 A5 A6 D A5 D A6 Q A1 Back to Back WRITEs DON T CARE UNDEFINED A...

Страница 24: ...ZZ I SUPPLY CLK ZZ t ZZREC ALL INPUTS except ZZ DON T CARE I DDZZ t ZZI tRZZI Outputs Q High Z DESELECT or READ Only Notes 30 Device must be deselected when entering ZZ mode See Truth Table 4 5 6 7 8...

Страница 25: ...ball Ball Grid Array 14 x 22 x 2 4 mm Pb Free CY7C1383F 133BGXI CY7C1381D 133BZI 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm CY7C1383D 133BZI CY7C1381D 133BZXI 51 85180 165 ball Fin...

Страница 26: ...TRUSION END FLASH SHALL NOT EXCEED 0 0098 in 0 25 mm PER SIDE 3 DIMENSIONS IN MILLIMETERS BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 0 30 0 08 0 65 20 00 0 10 22 00 0 20...

Страница 27: ...CY7C1381D CY7C1381F CY7C1383D CY7C1383F Document 38 05544 Rev F Page 27 of 29 Figure 2 119 ball BGA 14 x 22 x 2 4 mm 51 85115 Package Diagrams continued 51 85115 B Feedback...

Страница 28: ...a trademark of Intel Corporation All product and company names mentioned in this document are the trademarks of their respective holders Figure 3 165 ball FBGA 13 x 15 x 1 4 mm 51 85180 Package Diagr...

Страница 29: ...nd 6 2 C W respectively Changed JA and JC for FBGA Package from 46 and 3 C W to 20 7 and 4 0 C W respectively Modified VOL VOH test conditions Removed comment of Pb free BG packages availability below...

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