CY7C1346H
Document #: 38-05672 Rev. *B
Page 6 of 16
Truth Table
[2, 3, 4, 5, 6, 7]
Next Cycle
Add. Used
CE
1
CE
2
CE
3
ZZ
ADSP
ADSC
ADV
WRITE
OE
CLK
DQ
Deselect Cycle,
Power-down
None
H
X
X
L
X
L
X
X
X
L-H
Tri-State
Deselect Cycle,
Power-down
None
L
L
X
L
L
X
X
X
X
L-H
Tri-State
Deselect Cycle,
Power-down
None
L
X
H
L
L
X
X
X
X
L-H
Tri-State
Deselect Cycle,
Power-down
None
L
L
X
L
H
L
X
X
X
L-H
Tri-State
Deselect Cycle,
Power-down
None
L
X
H
L
H
L
X
X
X
L-H
Tri-State
Sleep Mode,
Power-down
None
X
X
X
H
X
X
X
X
X
X
Tri-State
READ Cycle,
Begin Burst
External
L
H
L
L
L
X
X
X
L
L-H
Q
READ Cycle,
Begin Burst
External
L
H
L
L
L
X
X
X
H
L-H
Tri-State
WRITE Cycle,
Begin Burst
External
L
H
L
L
H
L
X
L
X
L-H
D
READ Cycle,
Begin Burst
External
L
H
L
L
H
L
X
H
L
L-H
Q
READ Cycle,
Begin Burst
External
L
H
L
L
H
L
X
H
H
L-H
Tri-State
READ Cycle,
Continue Burst
Next
X
X
X
L
H
H
L
H
L
L-H
Q
READ Cycle,
Continue Burst
Next
X
X
X
L
H
H
L
H
H
L-H
Tri-State
READ Cycle,
Continue Burst
Next
H
X
X
L
X
H
L
H
L
L-H
Q
READ Cycle,
Continue Burst
Next
H
X
X
L
X
H
L
H
H
L-H
Tri-State
WRITE Cycle,
Continue Burst
Next
X
X
X
L
H
H
L
L
X
L-H
D
WRITE Cycle,
Continue Burst
Next
H
X
X
L
X
H
L
L
X
L-H
D
READ Cycle,
Suspend Burst
Current
X
X
X
L
H
H
H
H
L
L-H
Q
READ Cycle,
Suspend Burst
Current
X
X
X
L
H
H
H
H
H
L-H
Tri-State
READ Cycle,
Suspend Burst
Current
H
X
X
L
X
H
H
H
L
L-H
Q
READ Cycle,
Suspend Burst
Current
H
X
X
L
X
H
H
H
H
L-H
Tri-State
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write Enable signals (BW
A
,BW
B
,BW
C
,BW
D
) and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals
(BW
A
,BW
B
,BW
C
,BW
D
), BWE, GW = H.
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. CE
1
, CE
2
, and CE
3
are available only in the TQFP package.
6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW
[A:D]
. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to Tri-State. OE is a
don't care for the remainder of the Write cycle
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle all data bits are Tri-State when OE
is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
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