background image

CY7C1334H

Document #: 38-05678 Rev. *B

Page 12 of 13

© Cypress Semiconductor Corporation, 2006. The information contained herein is subject  to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device
Technology, Inc. All product and company names mentioned in this document are the trademarks of their respective holders.

 

Ordering Information

“Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or 

visit 

www.cypress.com

 for actual products offered”.

Speed

(MHz)

Ordering Code

Package
Diagram

Package Type

Operating

Range

166

CY7C1334H-166AXC

51-85050

100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

Commercial

CY7C1334H-166AXI

51-85050

100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

Industrial

133

CY7C1334H-133AXC

51-85050

100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

Commercial

CY7C1334H-133AXI

51-85050

100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

Industrial

Package Diagram

NOTE:

1. JEDEC STD REF MS-026

2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH

MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE

3. DIMENSIONS IN MILLIMETERS

BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH

0.30±0.08

0.65

20.00±0.10

22.00±0.20

1.40±0.05

12°±1°

1.60 MAX.

0.05 MIN.

0.60±0.15

0° MIN.

0.25

0°-7°

(8X)

STAND-OFF

R 0.08 MIN.

TYP.

0.20 MAX.

0.15 MAX.

0.20 MAX.

R 0.08 MIN.

0.20 MAX.

14.00±0.10

16.00±0.20

0.10

SEE DETAIL

A

DETAIL

A

1

100

30

31

50

51

80

81

GAUGE PLANE

1.00 REF.

0.20 MIN.

SEATING PLANE

100-pin TQFP (14 x 20 x 1.4 mm) (51-85050)

51-85050-*B

[+] Feedback 

Содержание CY7C1334H

Страница 1: ...quent Write Read transitions All synchronous inputs pass through input registers controlled by the rising edge of the clock All data outputs pass through output registers controlled by the rising edge...

Страница 2: ...DQA NC NC DQC DQC VDDQ VSSQ DQC DQC DQC DQC VSSQ VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSSQ DQD DQD DQD DQD VSSQ VDDQ DQD DQD NC A A CE 1 CE 2 BW D BW C BW B BW A CE 3 V DD V SS CLK WE CEN OE A A 1...

Страница 3: ...ins are tri stated and act as input data pins OE is masked during the data portion of a write sequence during the first clock when emerging from a deselected state when the device has been deselected...

Страница 4: ...sequence and will wrap around when incremented sufficiently A HIGH input on ADV LD will increment the internal burst counter regardless of the state of Chip Enables inputs or WE WE is latched at the b...

Страница 5: ...rst Next X L H X L X L L H Data In D NOP WRITE ABORT Begin Burst None L L L L H X L L H Tri State WRITE ABORT Continue Burst Next X L H X H X L L H Tri State IGNORE CLOCK EDGE Stall Current X L X X X...

Страница 6: ...H Write Bytes D A L L H H L Write Bytes D B L L H L H Write Bytes D B A L L H L L Write Bytes D C L L L H H Write Bytes D C A L L L H L Write Bytes D C B L L L L H Write All Bytes L L L L L ZZ Mode El...

Страница 7: ...for 3 3V I O 2 0 VDD 0 3V V for 2 5V I O 1 7 VDD 0 3V VIL Input LOW Voltage 9 for 3 3V I O 0 3 0 8 V for 2 5V I O 0 3 0 7 IX Input Leakage Current except ZZ and MODE GND VI VDDQ 5 5 A Input Current o...

Страница 8: ...llow standard test methods and procedures for measuring thermal impedance per EIA JESD51 30 32 C W JC Thermal Resistance Junction to Case 6 85 C W AC Test Loads and Waveforms Notes 11 Tested initially...

Страница 9: ...CLK Rise 0 5 0 5 ns tALH ADV LD Hold after CLK Rise 0 5 0 5 ns tWEH GW BW A D Hold after CLK Rise 0 5 0 5 ns tCENH CEN Hold after CLK Rise 0 5 0 5 ns tDH Data Input Hold after CLK Rise 0 5 0 5 ns tCE...

Страница 10: ...ce is determined by the status of the MODE 0 Linear 1 Interleaved Burst operations are optional WRITE D A1 1 2 3 4 5 6 7 8 9 CLK t CYC tCL tCH 10 CE tCEH tCES WE CEN tCENH tCENS BW A D ADV LD tAH tAS...

Страница 11: ...escription table for all possible signal conditions to deselect the device 23 I Os are in High Z when exiting ZZ sleep mode Switching Waveforms continued READ Q A3 4 5 6 7 8 9 10 CLK CE WE CEN BW A D...

Страница 12: ...d in this document are the trademarks of their respective holders Ordering Information Not all of the speed package and temperature ranges are available Please contact your local sales representative...

Страница 13: ...or Corporation on Page 1 from 3901 North First Street to 198 Champion Court Changed Three State to Tri State Modified Input Load to Input Leakage Current except ZZ and MODE in the Electrical Character...

Отзывы: