Cypress Semiconductor CY7C1246V18 Скачать руководство пользователя страница 2

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CY7C1246V18, CY7C1257V18
CY7C1248V18, CY7C1250V18

Document Number: 001-06348 Rev. *D

Page 2 of 27

Logic Block Diagram (CY7C1246V18)

Logic Block Diagram (CY7C1257V18)

CLK

(20:0)

Gen.

Control

Logic

Address

ead Add. Decode

Read Data Reg.

R/W

[7:0]

Output

Logic

Reg.

NWS

[1:0]

REF

rite Add. Decode

Control

2M x 8 A

rray

2M x 8 Arra

Write
Reg

R/W

DOFF

QVLD

CLK

(20:0)

Gen.

Control

Logic

Address

Read Add. De

code

Read Data Reg.

R/W

[8:0]

Output

Logic

Reg.

BWS

[0]

REF

rite Add. De

code

Control

2M x 9

Array

2M x 9 Arr

Write
Reg

R/W

DOFF

QVLD

[+] Feedback

Содержание CY7C1246V18

Страница 1: ...V18 are 1 8V Synchronous Pipelined SRAM equipped with DDR II architecture The DDR II consists of an SRAM core with advanced synchronous peripheral circuitry Addresses for read and write are latched on...

Страница 2: ...Data Reg R W DQ 7 0 Output Logic Reg Reg Reg 8 8 16 8 NWS 1 0 VREF Write Add Decode 8 8 LD Control 21 2M x 8 Array 2M x 8 Array Write Reg Write Reg CQ CQ R W DOFF QVLD 8 CLK A 20 0 Gen K K Control Lo...

Страница 3: ...W DQ 17 0 Output Logic Reg Reg Reg 18 18 36 18 BWS 1 0 VREF Write Add Decode 18 18 LD Control 20 1M x 18 Array 1M x 18 Array Write Reg Write Reg CQ CQ R W DOFF QVLD 18 CLK A 18 0 Gen K K Control Logic...

Страница 4: ...NC NC VSS NC DQ2 NC NC NC VREF NC NC VDDQ NC VDDQ NC NC VDDQ VDDQ VDDQ NC VDDQ NC DQ1 NC VDDQ VDDQ NC VSS NC NC NC TDI TMS VSS A NC A NC NC NC ZQ NC DQ0 NC NC NC NC A CY7C1257V18 4M x 9 2 3 4 5 6 7 1...

Страница 5: ...NC NC NC VREF NC DQ3 VDDQ NC VDDQ NC DQ5 VDDQ VDDQ VDDQ NC VDDQ NC DQ4 NC VDDQ VDDQ NC VSS NC NC NC TDI TMS VSS A NC A NC NC NC ZQ NC DQ2 NC DQ1 NC NC A CY7C1250V18 1M x 36 2 3 4 5 6 7 1 A B C D E F G...

Страница 6: ...8 0 and BWS1 controls D 17 9 CY7C1250V18 BWS0 controls D 8 0 BWS1 controls D 17 9 BWS2 controls D 26 18 and BWS3 controls D 35 27 All the Byte Write Selects are sampled on the same edge as the data De...

Страница 7: ...gh a 10 Kohm or less pull up resistor The device behaves in DDR I mode when the DLL is turned off In this mode the device can be operated at a frequency of up to 167 MHz with DDR I timing TDO Output T...

Страница 8: ...data flow such that 18 bits of data can be transferred into the device on every rising edge of the input clocks K and K When write access is deselected the device ignores all inputs after the pending...

Страница 9: ...he truth table for the CY7C1246V18 CY7C1257V18 CY7C1248V18 and CY7C1250V18 follows 2 3 4 5 6 7 Operation K LD R W DQ DQ Write Cycle Load address wait one cycle input write data on consecutive K and K...

Страница 10: ...7C1246V18 only the upper nibble D 7 4 is written into the device D 3 0 remains unaltered CY7C1248V18 only the upper byte D 17 9 is written into the device D 8 0 remains unaltered H L L H During the da...

Страница 11: ...y the byte D 17 9 is written into the device D 8 0 and D 35 18 remain unaltered H L H H L H During the data portion of a write sequence only the byte D 17 9 is written into the device D 8 0 and D 35 1...

Страница 12: ...dge of TCK Instruction Register Three bit instructions can be serially loaded into the instruction register This register is loaded when it is placed between the TDI and TDO pins as shown in TAP Contr...

Страница 13: ...ster After the data is captured it is possible to shift out the data by putting the TAP into the Shift DR state This places the boundary scan register between the TDI and TDO pins PRELOAD places an in...

Страница 14: ...ler follows 9 TEST LOGIC RESET TEST LOGIC IDLE SELECT DR SCAN CAPTURE DR SHIFT DR EXIT1 DR PAUSE DR EXIT2 DR UPDATE DR SELECT IR SCAN CAPTURE IR SHIFT IR EXIT1 IR PAUSE IR EXIT2 IR UPDATE IR 1 0 1 1 0...

Страница 15: ...GH Voltage 0 65VDD VDD 0 3 V VIL Input LOW Voltage 0 3 0 35VDD V IX Input and Output Load Current GND VI VDD 5 5 A 0 0 1 2 29 30 31 Boundary Scan Register Identification Register 0 1 2 108 0 1 2 Instr...

Страница 16: ...TDI Hold after Clock Rise 5 ns tCH Capture Hold after Clock Rise 5 ns Output Times tTDOV TCK Clock LOW to TDO Valid 10 ns tTDOX TCK Clock LOW to TDO Invalid 0 ns TAP Timing and Test Conditions Figure...

Страница 17: ...struction Codes Instruction Code Description EXTEST 000 Captures the input output ring contents IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO Thi...

Страница 18: ...35 10E 63 2A 91 3L 8 9R 36 10D 64 1A 92 1M 9 11P 37 9E 65 2B 93 1L 10 10P 38 10C 66 3B 94 3N 11 10N 39 11D 67 1C 95 3M 12 9P 40 9C 68 1B 96 1N 13 10M 41 9D 69 3D 97 2M 14 11N 42 11B 70 3C 98 3P 15 9M...

Страница 19: ...power and clock K K for 2048 cycles to lock the DLL DLL Constraints DLL uses K clock as its synchronizing input The input must have low phase jitter which is specified as tKC Var The DLL functions at...

Страница 20: ...0 1 mA Nominal Impedance VDDQ 0 2 VDDQ V VOL LOW Output LOW Voltage IOL 0 1 mA Nominal Impedance VSS 0 2 V VIH Input HIGH Voltage VREF 0 1 VDDQ 0 15 V VIL Input LOW Voltage 0 15 VREF 0 1 V IX Input L...

Страница 21: ...Ambient Test conditions follow standard test methods and procedures for measuring thermal impedance per EIA JESD51 16 25 C W JC Thermal Resistance Junction to Case 2 91 C W AC Test Loads and Waveform...

Страница 22: ...2 ns tCQDOH tCQHQX Echo Clock High to Data Invalid 0 2 0 2 0 2 ns tCQH tCQHCQL Output Clock CQ CQ HIGH 23 0 88 1 03 1 15 ns tCQHCQH tCQHCQH CQ Clock Rise to CQ Clock Rise 23 rising edge to rising edg...

Страница 23: ...OH QVLD t NOP DQ KHKH 12 Read Latency 2 0 Cycles NOP NOP CCQO tSD HD tSD tHD t CLZ t CHZ D20 D21 D30 D31 t CQDOH Q00 Q11 Q01 Q10 tDOH tCO Q40 Q41 tCQD t t tCQH CQHCQH Notes 28 Q00 refers to output fro...

Страница 24: ...all Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Industrial CY7C1257V18 375BZI CY7C1248V18 375BZI CY7C1250V18 375BZI CY7C1246V18 375BZXI 51 85195 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Pb...

Страница 25: ...00BZXC CY7C1246V18 300BZI 51 85195 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Industrial CY7C1257V18 300BZI CY7C1248V18 300BZI CY7C1250V18 300BZI CY7C1246V18 300BZXI 51 85195 165 ball Fine P...

Страница 26: ...Y7C1250V18 Document Number 001 06348 Rev D Page 26 of 27 Package Diagram Figure 6 165 ball FBGA 15 x 17 x 1 40 mm 51 85195 0 2 2 8 8 8 3 4 0 0 2 2 4 0 6 7 44 6 7 0 2 0 2 3 2 0 490 3 2 3 3 4 3 0 7 4 G...

Страница 27: ...e changes without further notice to the materials described herein Cypress does not assume any liability arising out of the application or use of any product or circuit described herein Cypress does n...

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