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CY7C1231H

Document #: 001-00207 Rev. *B

Page 6 of 12

Maximum Ratings

(Above which the useful life may be impaired. For user guide-
lines, not tested.)

Storage Temperature  ................................. –65°C to +150°C

Ambient Temperature with
Power Applied............................................. –55°C to +125°C

Supply Voltage on V

DD

 Relative to GND........ –0.5V to +4.6V

Supply Voltage on V

DDQ

 Relative to GND ...... –0.5V to +V

DD

DC Voltage Applied to Outputs
in Tri-State........................................... –0.5V to V

DDQ

 + 0.5V

DC Input Voltage ................................... –0.5V to V

DD

 + 0.5V

Current into Outputs (LOW)......................................... 20 mA

Static Discharge Voltage..........................................  > 2001V
(per MIL-STD-883, Method 3015)

Latch-up Current....................................................  > 200 mA

Operating Range

Range

Ambient

Temperature (T

A

)

V

DD

V

DDQ

Commercial

0°C to +70°C 

3.3V – 

5%/+10%

2.5V – 5% to 

V

DD

Industrial

-40°C to +85°C 

Electrical Characteristics

 

Over the Operating Range

[9,10]

Parameter

Description

Test Conditions

Min.

Max.

Unit

V

DD

Power Supply Voltage

3.135

3.6

V

V

DDQ

I/O Supply Voltage

for 3.3V I/O

3.135

V

DD

V

for 2.5V I/O

2.375

2.625

V

V

OH

Output HIGH Voltage

for 3.3V I/O, I

OH 

= –4.0 mA

2.4

V

for 2.5V I/O, I

OH 

= –1.0 mA

2.0

V

OL

Output LOW Voltage

for 3.3V I/O, I

OL 

= 8.0 mA

0.4

V

for 2.5V I/O, I

OL 

= 1.0 mA

0.4

V

IH

Input HIGH Voltage

for 3.3V I/O

2.0

V

DD

 + 0.3V

V

for 2.5V I/O

1.7

V

DD

 + 0.3V

V

IL

Input LOW Voltage

[9]

for 3.3V I/O

–0.3

0.8

V

for 2.5V I/O

–0.3

0.7

I

X

Input Leakage Current 
except ZZ and MODE

GND 

 V

I

 

 V

DDQ

–5

5

µ

A

Input Current of MODE

Input = V

SS

–30

µ

A

Input = V

DD

5

µ

A

Input Current of ZZ

Input = V

SS

–5

µ

A

Input = V

DD

30

µ

A

I

OZ

Output Leakage Current GND 

 V

I

 

 V

DDQ

, Output Disabled

–5

5

µ

A

I

DD

V

DD 

Operating Supply 

Current

V

DD 

= Max., I

OUT 

= 0 mA, 

f = f

MAX

= 1/t

CYC

7.5-ns cycle, 133 MHz

225

mA

I

SB1

Automatic CE 
Power-down 
Current—TTL Inputs 

V

DD 

= Max, Device Deselected, 

V

IN

 

 V

IH

 or V

IN

 

 V

IL

, f = f

MAX

inputs switching

7.5-ns cycle, 133 MHz

90

mA

I

SB2

Automatic CE 
Power-down 
Current—CMOS Inputs 

V

DD 

= Max, Device Deselected, 

V

IN

 

 V

DD

 – 0.3V or V

IN

 

 0.3V, 

f = 0, inputs static

7.5-ns cycle, 133 MHz

40

mA

I

SB3

Automatic CE 
Power-down 
Current—CMOS Inputs 

V

DD 

= Max, Device Deselected, 

V

IN

 

 V

DDQ 

– 0.3V or V

IN

 

 0.3V, 

f = f

MAX

, inputs switching

7.5-ns cycle, 133 MHz

75

mA

I

SB4

Automatic CE 
Power-down 
Current—TTL Inputs 

V

DD 

= Max, Device Deselected, 

V

IN

 

 V

DD 

– 0.3V or V

IN

 

 0.3V, 

f = 0, inputs static

7.5-ns cycle, 133 MHz

45

mA

Notes: 

9. Overshoot: V

IH

(AC) < V

DD

 

+1.5V (Pulse width less than t

CYC

/2), undershoot: V

IL

(AC)> –2V (Pulse width less than t

CYC

/2).

10. T

Power-up

: Assumes a linear ramp from 0V to V

DD

 

(min.) within 200 ms. During this time V

IH

 

< V

DD

 

and V

DDQ 

< V

DD

.

[+] Feedback 

Содержание CY7C1231H

Страница 1: ...g transferred on every clock cycle This feature dramatically improves the throughput of data through the SRAM especially in systems that require frequent Write Read transitions All synchronous inputs...

Страница 2: ...NC VSS VDDQ NC NC NC NC NC NC VDDQ VSS NC NC DQB DQB VSS VDDQ DQB DQB NC VDD NC VSS DQB DQB VDDQ VSS DQB DQB DQPB NC VSS VDDQ NC NC NC A A CE 1 CE 2 NC NC BW B BW A CE 3 V DD V SS CLK WE CEN OE NC 18...

Страница 3: ...uring the data portion of a write sequence during the first clock when emerging from a deselected state when the device has been deselected CEN Input Synchronous Clock Enable Input active LOW When ass...

Страница 4: ...HIGH input on ADV LD will increment the internal burst counter regardless of the state of Chip Enable inputs or WE WE is latched at the beginning of a burst cycle Therefore the type of access Read or...

Страница 5: ...READ Continue Burst Next X X X L H X X H L L H Tri State WRITE Cycle Begin Burst External L H L L L L L X L L H Data In D WRITE Cycle Continue Burst Next X X X L H X L X L L H Data In D NOP WRITE ABO...

Страница 6: ...H Voltage for 3 3V I O 2 0 VDD 0 3V V for 2 5V I O 1 7 VDD 0 3V VIL Input LOW Voltage 9 for 3 3V I O 0 3 0 8 V for 2 5V I O 0 3 0 7 IX Input Leakage Current except ZZ and MODE GND VI VDDQ 5 5 A Input...

Страница 7: ...ow standard test methods and procedures for measuring thermal impedance per EIA JESD51 30 32 C W JC Thermal Resistance Junction to Case 6 85 C W AC Test Loads and Waveforms Note 11 Tested initially an...

Страница 8: ...after CLK Rise 0 5 ns tWEH WE BW A B Hold after CLK Rise 0 5 ns tCENH CEN Hold after CLK Rise 0 5 ns tDH Data Input Hold after CLK Rise 0 5 ns tCEH Chip Enable Hold after CLK Rise 0 5 ns Notes 12 Tim...

Страница 9: ...nce is determined by the status of the MODE 0 Linear 1 Interleaved Burst operations are optional WRITE D A1 1 2 3 4 5 6 7 8 9 CLK tCYC tCL tCH 10 CE tCEH tCES WE CEN tCENH tCENS BW A B ADV LD tAH tAS...

Страница 10: ...uth Table for all possible signal conditions to deselect the device 23 I Os are in tri state when exiting ZZ sleep mode Switching Waveforms continued READ Q A3 4 5 6 7 8 9 10 A3 A4 A5 D A4 1 2 3 CLK C...

Страница 11: ...ZBT is a trademark of Integrated Device Technology Inc All product and company names mentioned in this document are the trademarks of their respective holders Ordering Information Not all of the spee...

Страница 12: ...conductor Corporation on Page 1 from 3901 North First Street to 198 Champion Court Removed 100 MHz Speed bin Changed Three State to Tri State Modified Input Load to Input Leakage Current except ZZ and...

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