Cypress Semiconductor CY7C1231H, Техническое описание

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CY7C1231H
Document #: 001-00207 Rev. *B Page 12 of 12
Document History Page
Document Title: CY7C1231H 2-Mbit (128K x 18) Flow-Through SRAM with NoBL™ Architecture
Document Number: 001-00207
REV. ECN NO. Issue Date
Orig. of
Change Description of Change
** 347377 See ECN PCI New Data Sheet
*A 428408 See ECN NXR Converted from Preliminary to Final.
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Removed 100 MHz Speed-bin
Changed Three-State to Tri-State.
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the
Electrical Characteristics Table.
Modified test condition from V
DDQ
< V
DD
to V
DDQ
<
V
DD
Replaced Package Name column with Package Diagram in the Ordering
Information table.
Updated the Ordering Information Table.
Replaced Package Diagram of 51-85050 from *A to *B
*B 459347 See ECN NXR Included 2.5V I/O option
Updated the Ordering Information table.
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