Cypress Semiconductor CY62167EV30, Техническое описание

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CY62167EV30 MoBL
®
Document #: 38-05446 Rev. *E Page 4 of 14
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters.
Parameter Description Test Conditions
VFBGA
(6 x 7 x 1mm)
VFBGA
(6 x 8 x 1mm)
TSOP I Unit
Θ
JA
Thermal Resistance
(Junction to Ambient)
Still Air, soldered on a 3 × 4.5 inch,
two-layer printed circuit board
27.74 55 60
°
C/W
Θ
JC
Thermal Resistance
(Junction to Case)
9.84 16 4.3
°
C/W
Shaded areas contain preliminary information.
Figure 3. AC Test Loads and Waveforms
Parameters 2.2V to 2.7V 2.7V to 3.6V Unit
R1 16667 1103
Ω
R2 15385 1554
Ω
R
TH
8000 645
Ω
V
TH
1.20 1.75 V
Data Retention Characteristics
Over the Operating Range
Parameter Description Conditions Min Typ
[5]
Max Unit
V
DR
V
CC
for Data Retention 1.5 V
I
CCDR
[10]
Data Retention Current V
CC
= 1.5V to 3.0V, CE
1
> V
CC
−
0.2V, CE
2
< 0.2V, V
IN
> V
CC
−
0.2V or V
IN
< 0.2V
Industrial/
Auto-A
-45ZXI
(TSOP I)
8
μ
A
V
CC
= 1.5V, CE
1
> V
CC
−
0.2V, CE
2
< 0.2V,
V
IN
> V
CC
−
0.2V or V
IN
< 0.2V
Industrial -45BAXI/
-45BVXI/
-45BVI
(VFBGA)
10
μ
A
t
CDR
[11]
Chip Deselect to Data
Retention Time
0 ns
t
R
[12]
Operation Recovery Time t
RC
ns
Figure 4. Data Retention Waveform
V
CC
V
CC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
Rise Time = 1 V/ns
Fall Time = 1 V/ns
OUTPUT V
Equivalent to: THÉVENIN EQUIVALENT
ALL INPUT PULSES
R
TH
R1
Notes
11. Tested initially and after any design or process changes that may affect these parameters.
12. Full device operation requires linear V
CC
ramp from V
DR
to V
CC
(min) > 100
μ
s or stable at V
CC
(min) > 100
μ
s.
13. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling the chip enable signals or by disabling both BHE and BLE.
V
CC
(min)
V
CC
(min)
t
CDR
V
DR
> 1.5 V
DATA RETENTION MODE
t
R
CE
1
or
V
CC
BHE
.
BLE
CE
2
or
[13]
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