CY14NVSRAMKIT-001 nvSRAM Development Kit User Guide, Doc. # 002-03522 Rev. *A
48
Kit Example Firmware
Update the Base Address to support the selected EBI and then initiate the EBI. The 165 FBGA
package is connected to the CS4 (chip select control 4) and the 54 TSOP II package is connected to
the CS3 (chip select control 3) of the FM4 MCU.
The following sections describe the changes to be made in the respective files.
6.3.1
Changes in
CY14B116.h
// CS3 TSOP
//#define nvSRAM_BASE_ADDRESS (0x63000000ul) // Uncomment to enable the
//base address for CS3 control
// CS4 FBGA
//#define nvSRAM_BASE_ADDRESS (0x64000000ul) // Uncomment to enable the
//base address for CS4 control
6.3.2
Changes in
CY14B116.c
nvSRAM_Init(uint8_t cycles) function
// CS3 TSOP
// return (Extif_InitArea(3u, &stcExtIF)); // Uncomment to return for CS3
// CS4 FBGA
// return (Extif_InitArea(4u, &stcExtIF)); // Uncomment to return for CS4
The sleep pin (ZZ#) is not available on the nvSRAM 54 TSOP II package. Hence, the Sleep and
Wakeup features, described in
Table 5-1 on page 34
, is not applicable for the 54 TSOP II package.
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