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FPDP PRIMER
Copyright 2012 10-5 FibreXtreme HW Reference for FPDP Cards
/DVALID are asserted. Since /SYNC is asserted at the end of a frame, the first
data frame transmitted will not be synchronized. As a result, the system designer
may wish to discard this first unsynchronized data frame. All data frames are the
same size when fixed size repeating frame data is transmitted.
DYNAMIC SIZE REPEATING FRAME DATA
•
Synchronization must occur prior to data to which it applies.
•
Synchronization occurs at the same time the last data word in the block before is
transferred.
•
/SYNC must be asserted at the end of the data block while /DVALID is still
asserted.
•
Because synchronization occurs at the end of the data block, the first data block
will not be synchronized.
•
Synchronization occurs frequently.
•
Data frames may vary in size.
For dynamic size repeating frame data, the behavior of the /SYNC pulse is the same as
for fixed size repeating frame data, with the exception of varying sized frames.
10.4 Serial FPDP Theory of Operation
The protocol and framing for Serial FPDP are listed in Appendix D. Serial FPDP
operates similar to parallel FPDP with respect to maintaining data framing with the
SYNC signal, but the SYNC signal does not correlate with data frames on the fiber. Any
form of data framing listed in section F.3.2 can be mapped to Serial FPDP, since the data
stream and SYNCs are maintained. However, the timing may not be exactly the same as
the parallel FPDP version due to link framing overhead and the fact that the link operates
asynchronously to the parallel FPDP frequencies.
10.5 Parallel FPDP Signal Timing
Figure 10-2 shows the timing for several FPDP interface signals. This figure is accurate
for all four data framing types. See section 10.3.2 for a discussion of framing. The Data
Valid signal, /DVALID, is asserted by the FPDP-TM when valid data is transmitted onto
the FPDP bus but not before at least 16 STROBE periods have occurred. The FPDP-TM
must de-assert /DVALID when no more data remains in its buffer until valid data is again
available. To avoid losing data when the receiver’s FIFO is almost full, the receiver
(FPDP-RM or FPDP-R) must assert the /SUSPEND signal to hold off the transmitter. The
FPDP-TM must de-assert /DVALID within 16 STROBE periods and keep it de-asserted
until /SUSPEND is de-asserted. Per the FPDP specification, after /SUSPEND is de-
asserted, the FPDP-TM must wait for at least one STROBE period before re-asserting
/DVALID. With the FibreXtreme SL240X card, after /SUSPEND is de-asserted, the
FPDP-TM must wait for at least two STROBE periods before re-asserting /DVALID. The
/SUSPEND signal is asynchronous to the STROBE clock and should be double
synchronized by the FPDP-TM before being used in order to avoid metastability
problems.
The FPDP-TM must not transmit data onto the FPDP bus until the Not Ready signal,
/NRDY, is de-asserted by the FPDP-RM and FPDP-R devices. The FPDP-RM and FPDP-
R devices must assert /NRDY when they are not ready to accept data and must de-assert
/NRDY otherwise. The /NRDY signal is asynchronous to the STROBE clock and should