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REGISTER SET
Copyright 2012 6-5 FibreXtreme HW Reference for FPDP Cards
Bit Description Access Reset
Value
topology (that is, two cards) because throughput will
decrease by a factor related to frame size.
15 to 13 Reserved None 0
16 Reset SR – Write ‘1’ to clear any latched status
information from the registers. Writing ‘0’ has no
effect. W 0
17 Clear SYNC without DVALID – Write ‘1’ to release a
FIFO stopped on SYNC without DVALID. Writing ‘0’
has no effect. W 0
18 Reserved None 0
19
Erase TX FIFO – Set to a ‘1’ to reset the Transmit
FIFO. This bit is included for testing and special
scenarios and, as such, should not be used in the
majority of applications. A hardware-level reset (e.g.,
the /RESET pin on the CMC connectors) performs a
reset of the entire SL100/SL240 FPGA logic, including
the FIFOs and is the only reset that should normally
be used. Resetting the Transmit FIFO or Receive
FIFO independently from the SL100/SL240 FPGA
logic can cause undesirable effects because each 32-
bit Serial FPDP data word occupies two entries in the
respective FIFO and the link and host are
independently filling and draining these FIFOs.
Applying the FIFO resets without applying special
precaution can result in a misalignment of data in
these FIFOs.
W 0
20
Erase RX FIFO – Set to a ‘1’ to reset the Receive
FIFO. This bit is included for testing and special
scenarios and, as such, should not be used in the
majority of applications. A hardware-level reset (e.g.,
the /RESET pin on the CMC connectors) performs a
reset of the entire SL100/SL240 FPGA logic, including
the FIFOs and is the only reset that should normally
be used. Resetting the Transmit FIFO or Receive
FIFO independently from the SL100/SL240 FPGA
logic can cause undesirable effects because each 32-
bit Serial FPDP data word occupies two entries in the
respective FIFO and the link and host are
independently filling and draining these FIFOs.
Applying the FIFO resets without applying special
precaution can result in a misalignment of data in
these FIFOs.
W 0
31 to 21 Reserved None 0