Adapter Tau-PCI/32, User Manual
Copyright © 2004-2007 Cronyx
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The transceiver provides exchange (reception/transmission) of information between
the “logical channels” and RAM via the PCI bus. The logical channels of the transceiver
are formed from the predefined E1 timeslots. Each timeslot can be "connected" to only
one logical channel. This allows up to 32 logical channels to be obtained. The exchange
of the data in the logical channel is a synchronous process that occurs at a speed
dependent on the number of the connected timeslots (unbalanced as an option). For each
logical channel, defined are a channel protocol (HDLC, transparent mode, etc.) and a
specific reception and transmission order; each channel can be started and suspended
independently of the others.
The on/off CAS signaling maintenance block allows you to implement associated
channel signaling processing adjusted for cross switching. The CAS maintenance block
exchanges data with the transceiver using timeslot 16, and, on the other hand, interacts
with the cross connector using a separate parallel data bus. The CAS maintenance block
is not included in the Tau-PCI/32-Lite, because its functionality becomes redundant and
unrequested with only one E1 interface available.
The nonblocking cross-connector allows you to set an “incoming” source for each
“outgoing” timeslot. This allows you to randomly switch and rearrange timeslots, provide
digital loops etc. The cross switching matrix is updated at the E1 frame border. In
addition to the data, the cross connector concurrently processes CAS signaling.
The use of the CAS maintenance block simultaneously to the activation of signaling
exchange at E1 interfaces produces full-value, three points cross switching of both
timeslots and CAS signaling.
An on/off switch of Sa-bits (Sa4 … Sa8) allows you to arrange
reception/transmission of Sa-bit values and enable them to be exchanged between E1
interfaces. The Sa-bit switch exchanges data with the transceiver via timeslot 0, and, on
the other hand, interacts directly with the E1 interfaces.
The on/off modules for supporting the unstructured mode for each E1 interface are
balanced type and controlled independently. The “unstructured” mode means that the E1
data flow does not have a frame structure according to ITU-T G.704, at the same time
data is transmitted in a synchronous bit flow at 2048 Kbps, and the borders of the
timeslots are not defined. Correspondingly, cross connector, CAS maintenance block and
Sa-bit switch become useless.
The activation of the unstructured mode at 2048 Kbps at one of the E1 interfaces (no
bit rate slow-down, see below) results in the engagement of all the transceiver timeslots.
The exchange of data with the other E1 interface and other functional blocks in the
adapter becomes impossible. Correspondingly, one logical channel for all timeslots must
be activated in the transceiver.
For compatibility with other equipment by Cronyx, the adapter supports scrambler
and multiple bit rate slow-down modes (2x, 4x, 8x, 16x and 32x). Simultaneously, the
physical data transmission rate always remains 2048 Kbps, only the useful transmission
rate changes.
