Contec DIO-32DM-PE, Руководство пользователя

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3. External Connection
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DIO-32DM-PE
External stop signal (EXTSTOP0/EXTSTOP1)
These input signals stop bus mastering with an external signal. The signal is LVTTL level and you can
select and enable the rising or falling edge with the software. In order to detect the signal edge, a high-
and low-level hold time of 50ns is needed at minimum.
Handshake Signal (EXTREQ0/EXTACK0/ EXTREQ1/EXTACK1)
These signals handshake with external devices. The signal is LVTTL level and controlled with
negative logic.
Input
Figure 3.8. Handshake Signals at the Time of Input
(1) After setting the handshaking operation, this product samples the EXTREQ0 signal and starts
pattern input when it recognizes a low pulse of more than 50ns. Pattern data prior to that time is
disabled.
(2) The board generates a cycle to write data input from an external device to the PC memory by bus
mastering.
(3) At the end of writing data, the board outputs acknowledge signal EXTRACK0 to notify the external
device.
Output
Figure 3.9. Handshake Signals at the Time of Output
(1) After setting the handshaking operation, this product outputs the EXTREQ1 signal.
(2) The board begins sampling acknowledge signals from external devices. The board recognizes the
end with a low pulse of more than 100ns and, at the leading edge, starts preparing to output the next
data.
EXTREQ0 (In)
DATA (In)
EXTACK0 (Out)
tREQIL : EXTREQ0 low width 50ns (Min.)
tACKOL : EXTACK0 low width 100ns
tHSIN : Handshaking time 100ns (Min.)
tHSIN
Invalid Valid
tACKOL
(2) (3)
(1)
tREQIL
EXTREQ1 (Out)
DATA (Out)
EXTACK1 (In)
tREQOL : EXTREQ1 low width 100ns
tACKOL : EXTACK1 low width 50ns (Min.)
Valid
tACKOL
(2)
(1)
tREQIL
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