Contec DIO-32DM-PE, Руководство пользователя

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3. External Connection
DIO-32DM-PE
41
Detailed Control Output Signal Circuit
Control signals to be output include handshake output signals.
Figure 3.5. Control signal output circuit
What is the Control Signal?
External clock signal (EXTCLK0/EXTCLK1)
These signals input external pacer clocks. The maximum frequency is 10MHz.
When the external clock input is set as the clock source, pattern input or output occurs at the falling
edge of this signal.
Figure 3.6. External clock signal
Eternal start signal (EXTSTART0/EXTSTART1)
These input signals start bus mastering with an external signal. The signal level is LVTTL and you
can select and enable the rising or falling edge with the software. In order to detect the signal edge, a
high- and low-level hold time of 50ns is needed at minimum.
Figure 3.7. External start signal
tPWH : Clock pulse high width 50ns (Min.)
tPWL : Clock pulse low width 50ns (Min.)
EXTCLK0
EXTCLK1
tPWH tPWL
tHIH : High level hold time 50ns (Min.)
tHIL : Low level hold time 50ns (Min.)
tHIH tHIL tHIH
EXTSTART0
EXTSTSRT1
SN74LV125A
Board
External circuit
GND
Output pin
EXTACK0
EXTREQ1
5V TTL IC or LVTTL IC