Connect Tech - Xtreme/Multi-I/O - Users Guide
Document: CTIM-00116
Revision: 0.02
0.02
Page 30 of 50
Connect Tech Inc. Proprietary Information
Date: Apr. 14, 2015
J1708 Bus Interface
Control Item
Address Offset
Command, Control, Status Registers
0x00
0x0F
Data FIFO’s
0x10
0x1F
Operation
The J1708 specification goes to significant detail about the requirements of the J1708 Bus interface, this
section elaborates on the specifics of
this
implementation of that interface. The J1708 specification should be
consulted to get a general sense of the nature of this communications protocol before continuing with the
description below.
The J1708 controller is implemented entirely in the FPGA. It consists of three (3) tightly coupled control
blocks; the Transmitter, Receiver and Interrupt Generator. The Transmitter and Receiver blocks share a
common Data Bit PLL clocking mechanism which clocks data bits at 9600 bps.
By its nature, the J1708 Bus is a ½ Duplex Bus, which causes any transmitted bits to also be received. It is this
behaviour that allows transmitted bytes to be checked for collisions with other bits being transmitted by other
device(s) on the J1708 Bus.
Receiver
The Receiver consists of a PLL clock recovery block, a control state machine, data bit shifting block and
controlling registers. The clock recovery block finds falling edges within the receive data stream and uses them
the align the phase of the data clock, in order to properly receive the data bits. This clock is also used by the
Transmitter.
Upon power up (or when the
Restart J1708 Bus SYNC
command is issued) the Receiver will begin hunting for
19 consecutive Bus
Idle
periods. During this time both the Receiver and Transmitter will not receive/send any
data bits. Once 19
Idles
are found the Receiver and Transmitter become operational.
Data bytes are framed in the usual asynchronous fashion, ie: 1-START bit, 8 data bits, 1-STOP bit.
When a legal START bit is detected, the following data bits are shifted into the Receiver data shift register
(only 8 bits are collected). The following bit is considered to be the STOP bit, and if it is legal (=1) the data
byte is placed into the FIFO.
Note:
Because the J1708 Bus is ½ duplex, any transmitted bits are also received. This implementation
can either store the transmitted bytes into the Receiver FIFO, or can mask (prevent) them from being
stored. This feature is controlled by the
Mask Reception of Good Transmitted Bytes
control bit. Refer to
the
Control Register
section below for more details. Even with this feature enabled, the Receiver
always receives the transmitted bits, so that error conditions in the Transmitter can be detected.
Messages
are groups of one or more data bytes that can be considered to belong together. Since there are no
delineating features in the data bytes themselves, the only feasible way to delineate (separate) received
messages is by determining when the J1708 Bus has gone
Idle
for a certain amount of time. The
RX EOM Level
register allows the host software to be notified when the desired Bus
Idle
interval has been reached (via and
interrupt), so that data can be retrieved from the Receiver FIFO.
Various Receiver conditions cause an interrupt to be generated. The situations/conditions that generate
interrupts are covered in more detail later in the
J1708 Interrupts
section, but are listed here for reference…
Receiver EOM (End of Message)
