Connect Tech - Xtreme/Multi-I/O - Users Guide
Document: CTIM-00116
Revision: 0.02
0.02
Page 31 of 50
Connect Tech Inc. Proprietary Information
Date: Apr. 14, 2015
Receiver FIFO Almost Full
Receiver FIFO Full
Transmitter
The Transmitter consists of a control state machine block, data bit shifting block, and controlling registers. It is
clocked by the Data Clock that is recovered by the Receiver. In this way the starting of a transmitted message
can be accurately timed from the end of the last message “seen” on the J1708 Bus. This accurate timing is the
essence of J1708 Bus messaging.
Transmission starts as soon as data byte(s) are written to the Transmitter FIFO, however the actual bit
transmission is delayed until after the J1708 Bus has been
Idle
for a certain amount of time. This time is
measured in Bit intervals from the end of the last message “seen” on the J1708 Bus. The duration of the delay
is controlled by the
TX Priority
register setting, and by a collision and re-transmission algorithm (which delays a
random number of Bus Idle periods). In special circumstances a user controlled delay can be setup (with the
User-Ta
register setting).
Software Implementation Note:
An alternate method to “kick off” Transmitter activity, is by using the
TX Kick
command, which causes the
TX FIFO Empty
interrupt to occur. In response to this interrupt, software can load data into the TX FIFO,
which causes the transmission to begin.
Transmission continues until one of 3 situations occur.
The Transmitter FIFO becomes empty.
An error is detected in the data bytes sent.
The software issues an
Abort TX
command.
Detecting Transmission Errors or Potential Problems
Since multiple devices can begin their bit transmissions at the same (or nearly same) point in time, there is a
variety of transmission issues that are detected and acted upon by the this J1708 controller. The detection is
possible because all transmitted bits are also received. At each byte boundary the byte sent is compared to the
byte received.
1.
In circumstances where there is heavy data traffic on the Bus, there may be situations where the
transmission of a message cannot begin because there is never a sufficiently long enough
Idle
period
on the bus. Each time a transmission is refused (preempted) by another transmission on the bus, this
condition is counted in a “TX Problem” counter. Also, if a collision occurs while the
first
byte of the
message is being transmitted, then again, this problem counter is incremented. This problem counter
value is compared against the
TX Problem Limit
register value. If the limit is reached an interrupt is
generated to the software. With the collision scenario, the Transmitter will again delay for the
required amount of
Idle
periods and attempt to re-send the message. This process repeats (forever)
until the transmission start is successful or software takes some action (in response to the problem
interrupt).
2.
In rare circumstances there may be a collision on the Bus
after
the first byte is successfully sent. In
this case the Transmitter self aborts as soon as the current byte is finished, the Transmitter FIFO is
flushed (emptied) and the
TX Abort
interrupt occurs.
This TX Problem counter is reset (to zero) when the
first
byte of a
new/next
message (packet) is
loaded from the FIFO into the TX data shift register.
Transmission Success
In the absence of any errors or commanded aborts, the Transmitter will continue sending data bytes until the
data FIFO is empty. When the last bit of the last byte is sent, this is the moment in time where the transmission
