ConMed sabre 180, Руководство по обслуживанию

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3-12
3.4 CONTROLLER HARDWARE
The Controller PWB Assembly is based on the
8031, a single chip, 8-bit microprocessor which
utilizes external program memory. Refer to
schematic, Figure 5.6a. This controller has the
following features.
1. Four 8-bit Ports (0,1,2,3) which are individual-
ly addressable as 32 Input/Output (I/O) lines.
2. Two 16-bit timer/event counters, one of which
is used as a software controlled tone generator via
the serial transmit pin TXD (U3 Pin 11).
3. Thirty-two (32)K bytes of externally address-
able program memory (A3U1), 128 bytes of
nonvolatile RAM (A3U2) for storage of calibra-
tion tables, and 256 bytes of serial EEPROM
(A2U4) for saving last used control settings.
4. One-chip oscillator and clock circuit which is
connected to an external 10 MHz clock signal
derived from a 20 MHz quartz time base (A3Y1).
5. One hundred and twenty-eight (128) bytes of
internal RAM used as a "scratch pad" by the
processor.
The remainder of the controller circuitry consists
of the Watchdog Timer (WDT), Power On Reset
(POR), Address Decoder, Peripheral Interface
Adapter (PIA), Base Voltage Generator (BVG),
Current Sensing Circuit, Waveform Generator
(WFG), Tone Generator, and the Aspen Return
Monitor (A.R.M.) DAC and current source.
The A3 Controller PWB is used for the SABRE
180 and Excalibur ESUs. The PWB is adapted for
each unit by installation of the appropriate
ROMS, Jumper TP20 and JMP1.
3.4.1 Watchdog Timer (WDT)
The function of this circuit is to monitor the
microprocessor for a failure that would cause
unpredictable results. During normal operation,
the microprocessor program executes in a known
sequence. If a software error is detected, an inter-
nal interrupt is generated which halts the opera-
tion of the microprocessor. If there is a hardware
failure sensed by software control, program execu-
tion will again be terminated.
Should a failure occur in the CPU that prevents
the detection of a problem, thus allowing pro-
gram execution in a random manner, the Sabre
180 is designed so that the WDT detects the
problem. The WDT shuts down the malfunction-
ing unit to minimize the effects of the failure.
This is accomplished by requiring the micro-
processor to write to the WDT once during each
program execution cycle. This write pulse is
referred to as the Watchdog Timer Strobe (WDT-
STB). Each cycle is 12 +/- 0.8 milliseconds long.
The WDT circuit must hear from the micro-
processor within a 10 to 15 msec window. If the
WDTSTB occurs early because the program
"skipped" a portion of the software or late because
it was "hung" in a program loop, the following
results:
1. The circuit latches in the failed condition so
that further strobing from the microprocessor
cannot clear the previous failure.
2. An interrupt (/WDTINT) is generated which
stops abnormal program execution. If the micro-
processor can still respond to the interrupt, a
"fatal" software routine will execute, displaying an
error code HLP - 4.
3. The interrupt signal /WDTINT, is used to gen-
erate /WDTFL, which disables the Base Voltage
Generator and Waveform Generator, preventing
further generation of RF output.
4. The MACHINE lamp on the front display
is illuminated by WDTFL which is also derived
from the interrupt, /WDTINT.
The Watchdog Timer (WDT) is made up of a
dual, retriggerable, one-shot multivibrator (U7),
associated RC timing components (R4, C5, R6,
and C6), the relay power enable register (U10),
and associated gates (U5 and U6). A WDTSTB
is generated whenever U10-2 and U10-3 are both
low. The first stage one-shot is set to time out at
the minimum WDTSTB interval of 10 msec by
the RC combination of R4 and C5. The trailing
(falling) edge of WDTSTB triggers the first stage
causing Q1 (U7-6) to go true (high) for approxi-
mately 10 msec. The rising edge of Q1 triggers
the second stage one-shot via U7-12, causing Q2
(U7-10) to go high and /Q2 (U7-9) to go low.
The 15 msec timing of this stage is set by the RC