Copyright
©
2012
congatec
AG
TCEDm10
48/94
Table 14 General Purpose I/O Signal Descriptions
Signal
Pin # Description
I/O
PU/PD
Comment
GPO0
A93
General purpose output pins.
Shared with SD_CLK. Output from COM Express, input to SD
O 3.3V
SDIO interface is not supported on the conga-TCA
GPO1
B54
General purpose output pins.
Shared with SD_CMD. Output from COM Express, input to SD
O 3.3V
SDIO interface is not supported on the conga-TCA
GPO2
B57
General purpose output pins.
Shared with SD_WP. Output from COM Express, input to SD
O 3.3V
SDIO interface is not supported on the conga-TCA
GPO3
B63
General purpose output pins.
Shared with SD_CD. Output from COM Express, input to SD
O 3.3V
SDIO interface is not supported on the conga-TCA
GPI0
A54
General purpose input pins. Pulled high internally on the module.
Shared with SD_DATA0. Bidirectional signal
I 3.3V
PU 10K 3.3V
SDIO interface is not supported on the conga-TCA
GPI1
A63
General purpose input pins. Pulled high internally on the module.
Shared with SD_DATA1. Bidirectional signal
I 3.3V
PU 10K 3.3V
SDIO interface is not supported on the conga-TCA
GPI2
A67
General purpose input pins. Pulled high internally on the module.
Shared with SD_DATA2. Bidirectional signal
I 3.3V
PU 10K 3.3V
SDIO interface is not supported on the conga-TCA
GPI3
A85
General purpose input pins. Pulled high internally on the module.
Shared with SD_DATA3. Bidirectional signal.
I 3.3V
PU 10K 3.3V
SDIO interface is not supported on the conga-TCA
Table 15 Power and System Management Signal Descriptions
Signal
Pin # Description
I/O
PU/PD
Comment
PWRBTN#
B12
Power button to bring system out of S5 (soft off), active on rising edge.
I 3.3VSB
PU 10k 3.3VSB
SYS_RESET#
B49
Reset button input. Active low input. Edge triggered.
System will not be held in hardware reset while this input is kept low.
I 3.3VSB
PU 10k 3.3VSB
CB_RESET#
B50
Reset output from module to Carrier Board. Active low. Issued by module chipset and may result
from a low SYS_RESET# input, a low PWR_OK input, a VCC_12V power input that falls below
the minimum specification, a watchdog timeout, or may be initiated by the module software.
O 3.3V
PD 100k
PWR_OK
B24
Power OK from main power supply. A high value indicates that the power
is good.
I 3.3V
Set by resistor divider
to accept 3.3V.
SUS_STAT#
B18
Indicates imminent suspend operation; used to notify LPC devices.
O 3.3VSB
SUS_S3#
A15
Indicates system is in Suspend to RAM state. Active-low output. An inverted copy of SUS_S3#
on the carrier board (also known as “PS_ON#”) may be used to enable the non-standby power
on a typical ATX power supply.
O 3.3VSB
SUS_S4#
A18
Indicates system is in Suspend to Disk state. Active low output.
O 3.3VSB
Not supported
SUS_S5#
A24
Indicates system is in Soft Off state.
O 3.3VSB
WAKE0#
B66
PCI Express wake up signal.
I 3.3VSB
PU 2.2k 3.3VSB
WAKE1#
B67
General purpose wake up signal. May be used to implement wake-up on PS/2 keyboard or
mouse activity.
I 3.3VSB
PU 2.2k 3.3VSB
BATLOW#
A27
Battery low input. This signal may be driven low by external circuitry to signal that the system
battery is low, or may be used to signal some other external power-management event.
I 3.3VSB
PU 10k 3.3VSB
