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Table 22
LPC Signal Descriptions
Signal
Pin # Description
I/O
PU/PD Comment
LPC_AD[0:3]
B4-B7
LPC multiplexed address, command and data bus
I/O 3.3V
PU 20k
LPC_FRAME#
B3
LPC frame indicates the start of an LPC cycle
O 3.3V
PU 20k
LPC_DRQ[0:1]#
B8-B9
LPC serial DMA request
I 3.3V
Not connected
LPC_SERIRQ
A50
LPC serial interrupt
I/O OD 3.3V PU 20k
LPC_CLK
B10
LPC clock output
O 3.3V
25MHz
Table 23
SPI Interface Signal Descriptions
Signal
Pin # Description
I/O
PU/PD Comment
SPI_CS# (**)
B97
Chip select for carrier board SPI.
O 3.3VSB
PU 100k
SPI_MISO (**)
A92
Master Input Slave Output: SPI output data from carrier board
SPI device to module.
I 3.3VSB
SPI_MOSI (**)
A95
Master Output Slave Input: SPI output data from module to
carrier board SPI.
O 3.3VSB
PD 100k
SPI_CLK (**)
A94
Clock from module to carrier board SPI BIOS flash.
O 3.3VSB
PD 100k
SPI_POWER
A91
Power source for carrier board SPI BIOS flash. SPI_POWER shall
be used to power SPI BIOS flash on the carrier only.
+ 3.3VSB
BIOS_DIS0#
A34
Selection strap to determine the BIOS boot device.
I 3.3VSB
PU 10k
3.3VSB
Carrier shall pull to GND or leave no-connect.
BIOS_DIS1#
B88
Selection strap to determine the BIOS boot device. Ground to
select external SPI device. Pull high or leave no-connect to select
on-module BIOS flash
I 3.3VSB
PU 10k
3.3VSB
Carrier shall pull to GND or leave no-connect
Note
On Intel Apollo Lake SoC, the signals marked with asterisks (**) have native voltage levels that are different from the levels defined in the
COM Express Specification. To comply with the COM Express Specification, the signals are routed through bidirectional level shifters on the
module. The bidirectional level shifters by nature have limited driving strenght. congatec therefore recommends that you route these signals
as short as possible.
