CMOSTEK NextGenRF CMT2189B, Руководство пользователя

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AN201
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9.3 Counter Mode of Timer 0
In this mode, the timer 0 increases by 1 when it is triggered by each rising or falling edge of the T0CKI pin (without prescaler).
Which edge to trigger is determined by the T0SE bit of the OPTION register. The software can set the T0CS bit of OPTION
register to 1 to enter the counter mode.
9.3.1 Prescaler Circuit Configurable by Software
The chip has a prescaler circuit in front of the Timer 0 and WDT timer, which can be assigned to Timer 0 or the WDT timer, but
they cannot use the prescaler at the same time. Whether assign to Timer0 or WDT is determined by the PSA bit of the OPTION
register. When PSA is 0, the prescaler is assigned to Timer 0. In the Timer 0 prescaler mode, there are 8 prescale ratios ( 1:2 to
1:256), which can be set by the PS<2:0> bit of the OPTION register.
Notes:
1. The prescaler circuit is neither readable nor writable. Any write operation on the TMR0 register will clear the prescaler
circuit.
2. When the prescaler circuit is assigned to the WDT, the prescaler circuit can be cleared by 1 CLRWDT instruction.
3. The prescaler circuit can be assigned to Timer 0 or the WDT timer, the prescaler switching between Timer 0 and WDT may
result in a false reset.
When switch the prescaler assignment from TMR0 to WDT, please execute the following instruction sequence.
When switch the prescaler assignment from the WDT to TMR0, please execute the following instruction sequence.
BANKSEL TMR0
CLRWDT
；
Clear WDT
CLRR TMR0
；
Clear TMR0 and prescaler
BANKSEL OPTION_REG
BSR OPTION_REG, PSA
；
Select WDT
CLRWDT
LDWI b
’11111000’ ；
Mask prescaler bits
ANDWR OPTION_REG, W
IORWI b
’00000101’
；
Set WDT prescaler to 1:32
LDWI OPTION_REG