CMT2300A
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Figure 8. Received signal jump diagram
The PJD mechanism defines that the input signal switching from 0 to 1 or from 1 to 0 is a phase jump. Users can configure the
PJD_WIN_SEL<1:0> to determine the number of detected jumps for the PJD to identify a wanted signal.As shown in the above
figure, in total 8 symbols are received. But the phase jump only appeared 6 times. Therefore, the number of jumpsis not equal to
the number of symbols. Only when a preamble is received theyare equal.In general, the more jumps are used to identify the
signal, the more reliable they result is; the less jumps are used, the faster the result is obtained.If the RX time is set to a relatively
short period, it is necessary to reduce the number of jumps to meet the timing requirements. Normally, 4 jumps allow pretty
reliable result, e.g. the chip will not mistakenly treat an incoming noise as a wanted signal, and vice versa will not treat a wanted
signal as noise.
Detecting the phase jump of a signal, is identical to detect whether the signal has the expecteddata rate. In fact, at the same time,
the PJD will also detect the FSK deviation and see if it is legal, as well as to see if the SNR is over 7 dB.With these three
parameters the PJD is able to make a very reliable judgement. If the signal is wanted it outputs logic 1, otherwise outputs logic 0.
The output can be used as a source of the RSSI VLD interrupt, or the receive time extending condition in the super low power
(SLP) mode. In direct data mode, by setting the DOUT_MUTE register bit to 1, the PJD can mute the FSK demodulated data
output while there is not wanted signal received.
The PJD technique is similar to the traditional carrier sense technique, but more reliable. While users combine the RSSI detection
and PJD technique, they can precisely identify the status of the current channel.
4.3.7 Automatic Frequency Control (AFC)
The AFC mechanism allows the receiver to minimize the frequency error between the TX and RX in a very short time once a
wanted signal comes in. This helps the receiver to maintain its highest sensitivity performance. CMT2300A has the most
advanced AFC technology. Compare with the other competitors, within the same bandwidth, CMT2300A can identify larger
frequency error, and remove the error in a much shorter time (8-10 symbols).
Normally the frequency error between the TX and RX is caused by the crystal oscillators used in both sides. CMT2300A allows
the user to fill in the value of crystal tolerance (in PPM) on RFPDK. Based on the crystal tolerance, the RFPDK will calculate the
AFC range whileminimizing the receiver bandwidth (to maintain the best performance). Due to the excellent performance of the
AFC, it provides a good solution to the crystal aging problem which would lead to more frequency error as time goes by.
Therefore, compare to other similar transceiver chips, CMT2300A can solve more severe crystal aging problem and effectively
extend the life time of the product.Please refer to “AN196-CMT2300A-CMT2219B-CMT2218B The Advantages of the Receiver
AFC.” for more details.
4.3.8 Clock Data Recovery (CDR)
The basic task of a CDR system is to recover the clock signal that is synchronized with the symbol rate, while receiving the data.
Not only for decoding inside the chip, but also for outputting the synchronized clock to GPIO for users to sample the data.So
CDR's task is simple and important. If the recovered clock frequency is in error with the actual symbol rate, it will cause data
acquisition errors at the time of reception.
CMT2300AW has designed three types of CDR systems, as follows:
1.
COUNTING system
–The system is designed for the symbol rates to be more accurate. If the symbol rate is 100% aligned,
the unlimited length of 0 can be received continuously without error.
