CMT2300A
Rev 1.0 | Page23/46
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VDD
0.9 V x (1 +/- 20%)
POR
< 0.2 us
Figure 5. Sudden Decrease of VDD lead to Generation of POR
The second case is, a slow decrease of the VDD. The POR triggering condition is, VDD decreases to 1.45V +/- 20% (e.g. 1.16V
– 1.74V) within a time more than or equal to 2 us. To be noticed, it detects an absolute value of VDD, not a decreasing amplitude.
VDD
1.45 V x (1 +/- 20%)
POR
> 0.2 us
Figure 6. Slow Decrease of VDD lead to Generation of POR
4.3.2 Crystal Oscillator
The crystal oscillator provides a reference clock for the phase locked loop as well as a system clock for the digital circuits. The
value of load capacitance depends on the crystal specified CL parameters. The total load capacitance between XI and XO should
be equal to CL, in order to make the crystal accurately oscillate at 26 MHz.
C15 and C16 are the load capacitancesat both ends of the crystal. Cpar is the parasitic capacitance on the PCB. Each crystal pin
has 5pF internal parasitic capacitance, together is equivalent to 2.5pF. The equivalent series resistance of the crystal must be
within the specifications so that the crystal can have a reliable vibration. Also, an external signal source can be connected to the
XI pin to replace the conventional crystal. The recommended peak value of this clock signal is from 300mV to 700mV. The clock
is coupled to XI pin via a blocking capacitor.
4.3.3 Sleep Timer
The CMT2300A integrates a sleep timer driven by 32 kHz low power oscillator (LPOSC). When this function is enabled, the timer
wakes the chip from sleep periodically. When the chip operates in a duty cycle mode, the sleep time can be configured from
0.03125 ms to 41922560 ms. Due to the low power oscillator frequency will change with the temperature and voltage drift, it will
