Cirrus Logic CS61880 Скачать руководство пользователя

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CDB61880

DS450DB1

6. BOARD CONFIGURATIONS

6.1 E1 75

Ω

Mode Setup

Table 4

shows the position of the different switches

and jumpers used to set up the CDB61880 evalua-

tion board to operate in E1 75

Ω

Hardware, Serial

Host and Parallel Host operational modes. Before
selecting Host mode, the switches in

Table 4

bold should be set to the position stated.

3. Connect a standard 25-pin male to female parallel port cable to connector J12 and the control PC.

4. Set “HIGH” to enable BITS Clock Recovery function for only Channel #0 in Hardware Mode.

5. Other settings may be used to enter G.772 Non-Intrusive Monitoring in Hardware Mode. Refer to the

CS61880 Data Sheet

for other settings.

6. Set “LOW” to disable receiver Internal line impedance matching function. The external resistors for all

eight receivers must be changed to 9.31

Ω

to properly match the input line impedance.

Table 4. E1 75

Ω

Operational Mode Switch/Jumper Position

Switches/Jumpers

Hardware

Serial Host (Note 3)

Parallel Host (Note 3)

S15 (MODE)

HARDWARE

SERIAL HOST

PARALLEL HOST

S1 (0)

LOOP FUNCTION

NONE

S2 (1)

LOOP FUNCTION

NONE

S3 (2)

LOOP FUNCTION

NONE

S4 (3)

LOOP FUNCTION

NONE

S5 (4)

LOOP FUNCTION

NONE

S6 (5)

LOOP FUNCTION

NONE

S7 (6)

LOOP FUNCTION

NONE

S8 (7)

LOOP FUNCTION

NONE

S9 #1 (MOT_\INTL)

HIGH

HIGH

MOTOROLA/INTEL

S9 #2 (MUX)

LOW (Note 4)

HIGH

MUX/NON-MUX

S9 #3 (A4)

LOW (Note 5)

HIGH

S9 #4 (A3)

LOW (Note 5)

HIGH

S9 #5 (A2)

LOW (Note 5)

HIGH

S9 #6 (A1)

LOW (Note 5)

HIGH

S9 #7 (A0)

LOW (Note 5)

HIGH

S10 (JASEL)

ANY POSITION

OPEN

S11 (CBLSEL)

HIGH (Note 6)

J13 (VLOGIC)

3 V

J1 (MCLK)

OSCILLATOR

J93 (CLKE)

OPEN

J23 (TXOE)

OPEN

Содержание CS61880

Страница 1: ...E1 75 Ω or E1 120 Ω The evaluation board can be operated in either Hard ware mode or Host mode In Hardware mode switches and bed stake headers are used to control the line con figuration and channel operations for all eight channels In Host mode Serial or Parallel the evaluation soft ware switches and bed stake headers are used to control the line configuration and operating mode set tings for eac...

Страница 2: ... to the terms and conditions of sale supplied at the time of order acknowledgment including those pertaining to warranty patent infringement and limitation of liability No responsibility is assumed by Cirrus for the use of this information including use of this information as the basis for manufacture or sale of any items or for infringement of patents or other rights of third parties This documen...

Страница 3: ...ator Selection 7 Figure 8 Loopback Mode Selection 7 Figure 9 Switch S9 Settings 8 Figure 10 Digital Signal Control Access 9 Figure 11 CS61884 Software Opening Screen 10 Figure 12 Register Bit Box 10 Figure 13 Set All Button 10 Figure 14 Clear All Button 11 Figure 15 Write All Button 11 Figure 16 Read All Button 11 Figure 17 Write Button 11 Figure 18 Read Button 11 Figure 19 Opening Screen for Port...

Страница 4: ...CDB61880 4 DS450DB1 1 CDB61880 EVALUATION BOARD LAYOUT Figure 1 CDB61880 Board Layout ...

Страница 5: ...oard logic to allow the current measurement to be made at the 3 V binding post 2 2 Master Clock Selection In both Hardware and Host modes the MCLK pin is configured by placing a short block on one of the positions of bed stake header J1 Figure 3 shows the different positions of the J1 bed stake header A 2 048 MHz clock oscillator is provided on the evaluation board for use as the on board clock so...

Страница 6: ...from each of the jumpers described in Table 2 To by pass the 1 KΩ resistors place a short block on each jumper shown in Table 2 The transmit line signals TTIP TRING from the device are coupled to the line binding post TXT 0 7 and TXR 0 7 through two octal transformers T1 and T9 External protection circuitry such as di odes or chokes are recommended for protection For further information on line pr...

Страница 7: ...In Hardware mode the Loopback modes are con figured with switches S1 through S8 0 7 Figure 8 shows the three different settings for all eight loop back switches In Host mode switches S1 through S8 must be set to the NONE middle position to allow host inter face control HI LO Enable all eight transmitters Hi Z all eight transmitters J23 TXO E HI LO TXO E J23 Figure 5 Transmitter Enable Selection J9...

Страница 8: ... switch block S9 When switches 3 through 7 inside switch block S9 are all set to the closed LOW position the G 772 Non Intrusive monitoring function is disabled Refer to the CS61880 Data Sheet for more address settings In Host mode switches 3 through 7 inside switch block S9 must be set to the open high position so that the host interface can have control over the ad dress signals during Parallel ...

Страница 9: ... through a standard 25 pin male to female parallel port cable No external µController board is required for host interface connection This connector is used for both serial and parallel interface 3 HOST SETUP DESCRIPTION Place the switches shown in Table 3 to the stated configuration before setting the Mode switch S15 to Serial or Parallel Host mode Refer to Figure 4 on page 6 for switch S15 setti...

Страница 10: ...Win dows 95 98 NT or 2000 Figure 11 shows the opening screen that appears after you have launched the software 4 2 Software Interface Buttons The following subsections explain the functions of buttons that are common to the register configura tion screens in the CS61880 software 4 2 1 Bit Indicator Description The Register Bit checkbox shown in Figure 12 shows one bit each register consists of eig...

Страница 11: ...t of every register on the current register screen This button is located in the bottom left cor ner of each register screen 4 4 Write Button Description The Write button shown in Figure 17 writes the bits of the corresponding register This button is lo cated to the right of every register that allows write access 4 5 Read Button Description The Read button shown in Figure 18 reads the bits of the...

Страница 12: ...l port address does not match the address of the control parallel port access to the register bits will not be permitted 5 2 Access and Configure the Read Write Registers You also use the opening screen to access the tabbed configuration screens for the Read Write Registers 5 2 1 Access Configuration Screens Click on the Read Write Registers button on the opening screen to start configuring these ...

Страница 13: ...Clock Screen The Loopback Bits Clock Register tabbed screen shown in Figure 20 allows access to the following registers Remote loop back Analog loop back Digital Loopback G 703 Bits Clock Figure 20 Loopback G 703 Bits Clock Selection Screen ...

Страница 14: ... access to the following registers LOS Status LOS Interrupt Enable LOS Interrupt Status LOS AIS Mode Enable DFM Status DFM interrupt Status DFM Interrupt Enable AIS Status AIS Interrupt Enable AIS Interrupt Status JA Error Interrupt Enable JA Error Interrupt Status Figure 21 LOS AIS DFM JA ERR Status Enable Selection Screen ...

Страница 15: ...wing registers Automatic TAOS TAOS Enable Performance Monitor Line Length Channel ID Line Length Data Output Disable NOTE Some indictor boxes bits in the Performance Monitor Line Length Channel ID and Line Length Data registers are grayed out this means that these bits can not be accessed Figure 22 Transmitter Register Screen ...

Страница 16: ...Phase Data The AWG Phase Address Register is broken up into two easy to use data input boxes the Chan Address i e channel address and the Sample Address For example to access the AWG func tion for channel 5 write 05 into the Chan Address input box This is the same for every channel The Chan Address Sample Address and Phase Data input boxes use the values discussed in the AWG section of the CS61880...

Страница 17: ...rectly to the bit in the Global Con trol Register on the top of this screen or by changing the radio buttons in one of the following windows Jitter Attenuator JA FIFO Length AWG Auto Increment Raisen Coden Jitter Corner Freq The variables listed above change the correspond ing bit in the Global Control Register The Soft ware Reset Register is a write only register and will clear after the write Th...

Страница 18: ...e matching function The external resistors for all eight receivers must be changed to 9 31 Ω to properly match the input line impedance Table 4 E1 75 Ω Ω Ω Ω Operational Mode Switch Jumper Position Switches Jumpers Hardware Serial Host Note 3 Parallel Host Note 3 S15 MODE HARDWARE SERIAL HOST PARALLEL HOST S1 0 LOOP FUNCTION NONE NONE S2 1 LOOP FUNCTION NONE NONE S3 2 LOOP FUNCTION NONE NONE S4 3 ...

Страница 19: ...Mode Switch Jumper Position Switches Jumpers Hardware Serial Host Note 3 Parallel Host Note 3 S15 MODE HARDWARE SERIAL HOST PARALLEL HOST S1 0 LOOP FUNCTION NONE NONE S2 1 LOOP FUNCTION NONE NONE S3 2 LOOP FUNCTION NONE NONE S4 3 LOOP FUNCTION NONE NONE S5 4 LOOP FUNCTION NONE NONE S6 5 LOOP FUNCTION NONE NONE S7 6 LOOP FUNCTION NONE NONE S8 7 LOOP FUNCTION NONE NONE S9 1 MOT_ INTL HIGH OPEN MOTOR...

Страница 20: ...onnect the CS61880 to one of the power supply binding post LED D3 will illuminate when jumper J13 is connected to a power supply Before selecting any Host mode place the CBLSEL LOOP ADDRESS and JASEL switches in the open or none position When using the CS61880 device in Internal Match Impedance mode be sure that the 1 KΩ resistors are not in series with the receivers ...

Страница 21: ... Notes ...

Страница 22: ......

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