Cirrus Logic CRYSTAL LAN CS890, Техническое справочное руководство

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AN83REV1 29
CS8900 Technical Reference Manual
SMEMWR* signals become active only for
the lower 1 Meg of the ISA address space.
The CHIPSEL* pin of the CS8900 should
be connected to ground.
2.3.2.2 Extended Memory mode
The CS8900 can also be mapped in to the
extended memory of a Personal Computer
(PC) system. This provides flexibility and
more options when several components are
installed in a PC with CS8900 based net-
work cards.
To address the CS8900 in extended mem-
ory mode, the processor is used in an en-
hanced mode. In an enhanced mode, 24
bits of ISA address lines are used for ad-
dress generation. Since the CS8900 ac-
cepts 20 bits of address lines, an external
address decoder circuit is required to de-
code the 4 upper address bits. The
CS8900 has interface pins for external de-
coder circuit.
This arrangement makes provisions so that
the CS8900 can be placed anywhere in the
extended memory address map as long as it
is at a 4K address boundary. The MEMR*
and MEMW* signals of the ISA bus are
active for any ISA memory space access,
therefore, for extended memory mode op-
eration, these signals are connected to the
MEMR* and MEMW* pins of the CS8900
respectively.
The external address decoder circuit con-
sists of a single and simple Programmable
Array Logic like a 16R4 or GAL16V8.
Please refer to the schematic shown in Fig-
ure 2.3.1 as an example of such a decoder
circuit. The PAL16R4 has 4 registers
Q[23:20]. These registers are programmed
by the serial input via the inputs EESK
(clock), ELCS* (enable pin) and EEDa-
taOut (serial data out). This decoder com-
pares the 4 upper address bits, namely
LA[23:20], with the internal programmable
register, Q[23:20]. Before memory mode
of the CS8900 is enabled, Q[23:20] must
be initialized to a proper value.
In the design example, Q[23:20] form a left
shift register. The ELCS* pin of the
CS8900 is used in-conjunction with EESK
and EEDataOut pins to shift in the data for
Q[23:20] serially. To program a value, set
the ELSEL bit (bit A in Packet Page base +
040h) to HIGH. Then the EEPROM inter-
face is used to generate the serial data
stream on EEDataOut pin (serial data out)
with the EESK (serial clock). Whenever
ELSEL bit is set, ELCS* pin becomes ac-
tive (LOW) instead of EECS* pin during
the EEPROM operations. Since the EECS*
pin remains inactive, the EEPROM that is
interfaced to the CS8900 is not enabled.
For the PAL in the design example, one
should use a “Program disable” EEPROM
command. (Opcode 00000b). For exam-
ple, if the CS8900 is to be placed at PC
memory space of 0A00000h, that means
the Q[23:20] should be 0Ah. To program
the 16R4, write 040Ah at Packet Page Base
+ 040h. The instruction will take about 10
micro-seconds to execute.
The electrical connections required to use
external logic are shown in Figure 2.5.1.
At reset, the CS8900 samples ELCS* pin
and if it is not "LOW", it realizes presence
of external address decode logic. The same
reset signal also makes ADD_VALID inac-
tive, and thus prevents a signal CHIP-
SEL_b from becoming active until
Q[23:20] are initialized. When a host CPU