Cirrus Logic ARM CDB89712, Руководство пользователя

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CDB89712
DS502UM2 3-3
3.4.2 FLASH Memory
The FLASH memory is provided in one bank, made up of two 32 Mbit devices, arranged as one
contiguous block of 8 Mbytes. Accesses to FLASH are 32 bits wide.
The devices used on the development board are Intel TE28F320B3BA110.
Each block may be erased up to 100,000 times before end of life. If frequent writes to FLASH are
likely, the life of the FLASH memory can be extended by distributing data storage over the entire
addressable space of the FLASH memory.
The FLASH devices have 110nS access time. When running at 73.728MHz, a minimum of 5 wait-
states is required to reliably communicate with the FLASH memory.
Details on erasing, writing, locking and unlocking the sectors of the FLASH devices can be found
in the Intel data sheet for the L28F320 FLASH devices, Intel Order Number 290645-009. A
reference datasheet is provided on the CD, l28f320.pdf.
3.5 CS89712 CLOCKS
The CS89712 requires two clocks for normal operation:
l
The main system clock (default clock)
l
The real time clock
The real-time clock oscillates at a frequency of 32.768 KHz. This clock provides the time base for
the integrated real time clock and is provided by a simple tuning fork type crystal.
The processor derives its clock from a 3.6864 MHz crystal connected to the master oscillator pins.
73.728 MHz is the maximum operating frequency of the CS89712.
3.6 POWER MANAGEMENT MODES
The power management modes implemented by the CS89712 enable complete control of system
power consumption. While the development board does not actually implement power management
features, it does provide access to the CS89712’s power management signals. This allows power
management functionality to be tested and verified.
The four signals that control the power management of the CS89712 are:
l
nEXTPWR
l
nPWRFL
l
BATOK
l
nBATCHG
Four switches positioned at the edge of the board control these signals. These switches allow various
transitions to be made between the operating states of the CS89712.
Figure 4-13 shows the switch
state for each of the following signals.
3.6.1 Description of Power Management Signals
Here is a brief explanation of the four power management signals.
3.6.1.1. BATOK
When asserted indicates a battery failure condition. A falling edge on the BATOK signal generates
a FIQ. This condition would initiate a transition to Standby State.
The CS89712 will only transition to the Operating State if both BATOK and nPWRFL are returned