EGS5 Hardware Interface Description
2.3 Circuit Concept
23
EGS5_HD_v02.004
Page 23 of 123
2012-02-09
Confidential / Released
2.3
Circuit Concept
shows a block diagram of the EGS5 module and illustrates the major functional com-
ponents:
Baseband block:
•
Digital baseband processor with DSP
•
Analog processor with power supply unit (PSU)
•
Flash / SRAM (stacked)
•
Application interface (SMT with connecting pads)
RF section:
•
RF transceiver
•
RF power amplifier
•
RF front end
•
Antenna pad
Figure 2:
EGS5
block diagram
BATT+
GND
IGT
EMERG_OFF
ASC (0)
SIM Interface
D(0:15)
A(0:24)
RD; WR; CS; WAIT
Interface
RF -
Baseband
NTC
BATT_TEMP
VDDLP
SYNC
RF
Transceiver
RF
Power Amplifier
PSRAM
Nor-Flash
Audio analog
ADC2_IN
DAC_OUT
USB
GPIO
SPI
VEXT
ISENSE
VSENSE
VCHARGE
CHARGEGATE
TEMP 1
REFCHG
ASC (1)
26
MHz
RF
Front End
DAI
PWR_IND
Measuring
Network
32.768
kHz
26 MHz
Ap
pl
ic
at
io
n In
te
rf
ac
e
Digital and Analog
Baseband Processor
Conversion
Switch
TEMP 2
BATTEMP
AUXADC 1
ADC1_IN
Several
power supply
voltages
I2C/SPI